Tom Stellard 9638ce5c6d Merging r238147: ...

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r238147 | thomas.stellard | 2015-05-25 12:15:54 -0400 (Mon, 25 May 2015) | 4 lines

R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips

The src and dst register cannot be the same on chips with 16 lds banks.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@240285 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-22 14:58:20 +00:00

..

AArch64

Merging r236457 and r236635:

2015-06-12 15:57:35 +00:00

ARM

Merging r228518:

2015-02-09 02:38:04 +00:00

CPP

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

Generic

CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.

2014-12-19 20:50:07 +00:00

Hexagon

Merging r226048:

2015-01-15 04:04:08 +00:00

Inputs

Merging r226048:

2015-01-15 04:04:08 +00:00

Mips

Revert r235869 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.

2015-05-15 10:05:22 +00:00

MSP430

…

NVPTX

Check that the TLI callback enableAggressiveFMAFusion has the desired effect on FMA folding.

2015-01-14 15:36:28 +00:00

PowerPC

Merging r228969:

2015-02-12 23:51:24 +00:00

R600

Merging r238147:

2015-06-22 14:58:20 +00:00

SPARC

Revert r225957 from the 3.6 branch.

2015-01-17 00:43:31 +00:00

SystemZ

Use the integrated assembler as default on SystemZ

2015-01-13 19:45:16 +00:00

Thumb

Merging r226048:

2015-01-15 04:04:08 +00:00

Thumb2

[ARM] Fix a bug in constant island pass that was triggering an assertion.

2015-01-08 20:44:50 +00:00

X86

Merging r227519:

2015-05-02 04:17:29 +00:00

XCore

Merging r226048:

2015-01-15 04:04:08 +00:00