llvm-6502/lib/CodeGen
2010-07-19 18:47:01 +00:00
..
AsmPrinter Fix PR 7662. 2010-07-19 17:53:55 +00:00
PBQP Iterating over sets of pointers in a heuristic was a bad idea. Switching 2010-07-17 06:31:41 +00:00
SelectionDAG Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. 2010-07-19 18:47:01 +00:00
AggressiveAntiDepBreaker.cpp Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. This time 2010-07-15 19:58:14 +00:00
AggressiveAntiDepBreaker.h Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. 2010-07-15 18:43:09 +00:00
Analysis.cpp Split -enable-finite-only-fp-math to two options: 2010-07-15 22:07:12 +00:00
AntiDepBreaker.h
BranchFolding.cpp
BranchFolding.h
CalcSpillWeights.cpp Remove remaining calls to TII::isMoveInstr. 2010-07-16 21:03:55 +00:00
CallingConvLower.cpp Reapply bottom-up fast-isel, with several fixes for x86-32: 2010-07-10 09:00:22 +00:00
CMakeLists.txt Update CMake build. 2010-07-19 15:37:03 +00:00
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. This time 2010-07-15 19:58:14 +00:00
CriticalAntiDepBreaker.h Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. This time 2010-07-15 19:58:14 +00:00
DeadMachineInstructionElim.cpp
DwarfEHPrepare.cpp Use the catch-all selectors we already found when converting them to use the 2010-06-30 22:49:53 +00:00
ELF.h Get rid of a bunch of duplicated ELF enum values. 2010-07-16 07:53:29 +00:00
ELFCodeEmitter.cpp Get rid of a bunch of duplicated ELF enum values. 2010-07-16 07:53:29 +00:00
ELFCodeEmitter.h
ELFWriter.cpp Get rid of a bunch of duplicated ELF enum values. 2010-07-16 07:53:29 +00:00
ELFWriter.h Get rid of a bunch of duplicated ELF enum values. 2010-07-16 07:53:29 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp use ArgOperand API and CallSite to access arguments of CallInst 2010-06-25 08:48:19 +00:00
IfConversion.cpp Reapply my if-conversion cleanup from svn r106939 with fixes. 2010-06-29 00:55:23 +00:00
InlineSpiller.cpp Spillers may alter MachineLoopInfo when breaking critical edges, so make it 2010-07-19 18:41:20 +00:00
IntrinsicLowering.cpp use CallSite::arg_end instead of CallInst::op_end 2010-06-30 12:39:23 +00:00
LatencyPriorityQueue.cpp
LiveInterval.cpp Print VNInfo flags. 2010-07-13 21:19:05 +00:00
LiveIntervalAnalysis.cpp Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. 2010-07-16 04:45:42 +00:00
LiveStackAnalysis.cpp VNInfos don't need to be destructed anymore. 2010-06-26 11:30:59 +00:00
LiveVariables.cpp
LLVMTargetMachine.cpp Reapply bottom-up fast-isel, with several fixes for x86-32: 2010-07-10 09:00:22 +00:00
LowerSubregs.cpp Convert EXTRACT_SUBREG to COPY when emitting machine instrs. 2010-07-08 16:40:22 +00:00
MachineBasicBlock.cpp Add a getFirstNonPHI utility function. 2010-07-07 14:33:51 +00:00
MachineCSE.cpp Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. 2010-07-16 04:45:42 +00:00
MachineDominators.cpp
MachineFunction.cpp Fix debugging strings. 2010-07-07 17:28:45 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG. 2010-07-04 23:24:23 +00:00
MachineLICM.cpp Teach ProcessImplicitDefs to transform more COPY instructions into IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620. 2010-07-14 01:22:19 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp Revert r108369, sorting llvm.dbg.declare information by source position, 2010-07-16 17:54:27 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel. 2010-07-10 22:42:59 +00:00
MachineSink.cpp - Reapply r106066 now that the bzip2 build regression has been fixed. 2010-06-25 20:48:10 +00:00
MachineSSAUpdater.cpp
MachineVerifier.cpp
Makefile
ObjectCodeEmitter.cpp Remove accidental commited comment 2009-08-05 07:00:43 +00:00
OcamlGC.cpp
OptimizeExts.cpp Convert EXTRACT_SUBREG to COPY when emitting machine instrs. 2010-07-08 16:40:22 +00:00
OptimizePHIs.cpp Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. 2010-07-16 04:45:42 +00:00
Passes.cpp
PHIElimination.cpp Emit COPY instructions instead of using copyRegToReg in InstrEmitter, 2010-07-10 19:08:25 +00:00
PHIElimination.h
PostRAHazardRecognizer.cpp
PostRASchedulerList.cpp Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. 2010-07-15 20:01:02 +00:00
PreAllocSplitting.cpp Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. 2010-07-16 04:45:42 +00:00
ProcessImplicitDefs.cpp Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. 2010-07-16 04:45:42 +00:00
PrologEpilogInserter.cpp Clean up scavengeRegister() a bit to prefer available regs, which allows 2010-07-08 16:49:26 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocFast.cpp Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. 2010-07-16 04:45:42 +00:00
RegAllocLinearScan.cpp Spillers may alter MachineLoopInfo when breaking critical edges, so make it 2010-07-19 18:41:20 +00:00
RegAllocPBQP.cpp Render MachineFunctions to HTML pages, with options to render register 2010-07-19 15:22:28 +00:00
RegisterCoalescer.cpp Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. 2010-07-16 04:45:42 +00:00
RegisterScavenging.cpp Clean up scavengeRegister() a bit to prefer available regs, which allows 2010-07-08 16:49:26 +00:00
RenderMachineFunction.cpp Render MachineFunctions to HTML pages, with options to render register 2010-07-19 15:22:28 +00:00
RenderMachineFunction.h Render MachineFunctions to HTML pages, with options to render register 2010-07-19 15:22:28 +00:00
ScheduleDAG.cpp Remove trailing whitespace, no functionality changes. 2010-06-30 03:40:54 +00:00
ScheduleDAGEmit.cpp Emit COPY instructions instead of using copyRegToReg in InstrEmitter, 2010-07-10 19:08:25 +00:00
ScheduleDAGInstrs.cpp Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. 2010-07-15 20:04:36 +00:00
ScheduleDAGInstrs.h When processing loops for scheduling latencies (used for live outs on loop 2010-06-29 04:48:13 +00:00
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp use ArgOperand API and CallSite to access arguments of CallInst 2010-06-25 08:48:19 +00:00
ShrinkWrapping.cpp
SimpleRegisterCoalescing.cpp Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. 2010-07-16 04:45:42 +00:00
SimpleRegisterCoalescing.h Be more forgiving when calculating alias interference for physreg coalescing. 2010-07-06 20:31:51 +00:00
SjLjEHPrepare.cpp Handle array and vector typed parameters in sjljehprepare like we do 2010-06-30 22:20:38 +00:00
SlotIndexes.cpp Print the LSBs of a SlotIndex symbolically using letters referring to the 2010-06-24 17:31:07 +00:00
Spiller.cpp Spillers may alter MachineLoopInfo when breaking critical edges, so make it 2010-07-19 18:41:20 +00:00
Spiller.h Spillers may alter MachineLoopInfo when breaking critical edges, so make it 2010-07-19 18:41:20 +00:00
Splitter.cpp Removed unused inRange variable. 2010-07-17 11:43:07 +00:00
Splitter.h Fix struct/class mismatch 2010-07-18 11:47:56 +00:00
StackProtector.cpp tighten up this code. 2010-07-06 15:59:27 +00:00
StackSlotColoring.cpp Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel. 2010-07-10 22:42:59 +00:00
StrongPHIElimination.cpp Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel. 2010-07-10 22:42:59 +00:00
TailDuplication.cpp Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. 2010-07-16 04:45:42 +00:00
TargetInstrInfoImpl.cpp Don't add memory operands to storeRegToStackSlot / loadRegFromStackSlot results, 2010-07-13 00:23:30 +00:00
TargetLoweringObjectFileImpl.cpp fix the definitions of ConstTextCoalSection/ConstDataCoalSection 2010-07-15 21:22:00 +00:00
TwoAddressInstructionPass.cpp Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. 2010-07-16 04:45:42 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp
VirtRegMap.h
VirtRegRewriter.cpp Remove remaining calls to TII::isMoveInstr. 2010-07-16 21:03:55 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.