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968e1f2f5b
Currently this only functions to match simple cases where ds_read2_* / ds_write2_* instructions can be used. In the future it might match some of the other weird load patterns, such as direct to LDS loads. Currently enabled only with a subtarget feature to enable easier testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219533 91177308-0d34-0410-b5e6-96231b3b80d8
376 lines
12 KiB
C++
376 lines
12 KiB
C++
//===-- SILoadStoreOptimizer.cpp ------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass tries to fuse DS instructions with close by immediate offsets.
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// This will fuse operations such as
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// ds_read_b32 v0, v2 offset:16
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// ds_read_b32 v1, v2 offset:32
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// ==>
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// ds_read2_b32 v[0:1], v2, offset0:4 offset1:8
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//
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//
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// Future improvements:
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//
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// - This currently relies on the scheduler to place loads and stores next to
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// each other, and then only merges adjacent pairs of instructions. It would
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// be good to be more flexible with interleaved instructions, and possibly run
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// before scheduling. It currently missing stores of constants because loading
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// the constant into the data register is placed between the stores, although
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// this is arguably a scheduling problem.
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//
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// - Live interval recomputing seems inefficient. This currently only matches
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// one pair, and recomputes live intervals and moves on to the next pair. It
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// would be better to compute a list of all merges that need to occur
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//
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// - With a list of instructions to process, we can also merge more. If a
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// cluster of loads have offsets that are too large to fit in the 8-bit
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// offsets, but are close enough to fit in the 8 bits, we can add to the base
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// pointer and use the new reduced offsets.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "SIInstrInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-load-store-opt"
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namespace {
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class SILoadStoreOptimizer : public MachineFunctionPass {
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private:
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const TargetMachine *TM;
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const SIInstrInfo *TII;
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const SIRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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LiveIntervals *LIS;
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static bool offsetsCanBeCombined(unsigned Offset0,
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unsigned Offset1,
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unsigned EltSize);
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MachineBasicBlock::iterator findMatchingDSInst(MachineBasicBlock::iterator I,
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unsigned EltSize);
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void updateRegDefsUses(unsigned SrcReg,
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unsigned DstReg,
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unsigned SubIdx);
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MachineBasicBlock::iterator mergeRead2Pair(
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
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unsigned EltSize,
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const MCInstrDesc &Read2InstDesc);
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MachineBasicBlock::iterator mergeWrite2Pair(
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
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unsigned EltSize,
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const MCInstrDesc &Write2InstDesc);
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public:
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static char ID;
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SILoadStoreOptimizer() :
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MachineFunctionPass(ID),
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TM(nullptr),
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TII(nullptr),
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TRI(nullptr),
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MRI(nullptr),
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LIS(nullptr) {
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}
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SILoadStoreOptimizer(const TargetMachine &TM_) :
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MachineFunctionPass(ID),
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TM(&TM_),
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TII(static_cast<const SIInstrInfo*>(TM->getSubtargetImpl()->getInstrInfo())) {
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initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
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}
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bool optimizeBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "SI Load / Store Optimizer";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addPreserved<SlotIndexes>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreserved<LiveVariables>();
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AU.addRequired<LiveIntervals>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(SILoadStoreOptimizer, DEBUG_TYPE,
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"SI Load / Store Optimizer", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(LiveVariables)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_END(SILoadStoreOptimizer, DEBUG_TYPE,
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"SI Load / Store Optimizer", false, false)
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char SILoadStoreOptimizer::ID = 0;
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char &llvm::SILoadStoreOptimizerID = SILoadStoreOptimizer::ID;
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FunctionPass *llvm::createSILoadStoreOptimizerPass(TargetMachine &TM) {
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return new SILoadStoreOptimizer(TM);
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}
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bool SILoadStoreOptimizer::offsetsCanBeCombined(unsigned Offset0,
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unsigned Offset1,
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unsigned EltSize) {
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// XXX - Would the same offset be OK? Is there any reason this would happen or
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// be useful?
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return (Offset0 != Offset1) &&
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isUInt<8>(Offset0 / EltSize) &&
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isUInt<8>(Offset1 / EltSize);
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}
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MachineBasicBlock::iterator
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SILoadStoreOptimizer::findMatchingDSInst(MachineBasicBlock::iterator I,
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unsigned EltSize){
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MachineBasicBlock::iterator E = I->getParent()->end();
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MachineBasicBlock::iterator MBBI = I;
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++MBBI;
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if (MBBI->getOpcode() != I->getOpcode())
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return E;
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// Don't merge volatiles.
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if (MBBI->hasOrderedMemoryRef())
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return E;
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int AddrIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::addr);
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const MachineOperand &AddrReg0 = I->getOperand(AddrIdx);
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const MachineOperand &AddrReg1 = MBBI->getOperand(AddrIdx);
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// Check same base pointer. Be careful of subregisters, which can occur with
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// vectors of pointers.
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if (AddrReg0.getReg() == AddrReg1.getReg() &&
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AddrReg0.getSubReg() == AddrReg1.getSubReg()) {
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int OffsetIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(),
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AMDGPU::OpName::offset);
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unsigned Offset0 = I->getOperand(OffsetIdx).getImm();
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unsigned Offset1 = MBBI->getOperand(OffsetIdx).getImm();
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// Check both offsets fit in the reduced range.
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if (offsetsCanBeCombined(Offset0, Offset1, EltSize))
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return MBBI;
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}
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return E;
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}
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void SILoadStoreOptimizer::updateRegDefsUses(unsigned SrcReg,
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unsigned DstReg,
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unsigned SubIdx) {
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for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg),
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E = MRI->reg_end(); I != E; ) {
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MachineOperand &O = *I;
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++I;
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O.substVirtReg(DstReg, SubIdx, *TRI);
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}
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}
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MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair(
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
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unsigned EltSize,
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const MCInstrDesc &Read2InstDesc) {
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MachineBasicBlock *MBB = I->getParent();
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// Be careful, since the addresses could be subregisters themselves in weird
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// cases, like vectors of pointers.
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const MachineOperand *AddrReg = TII->getNamedOperand(*I, AMDGPU::OpName::addr);
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unsigned DestReg0 = TII->getNamedOperand(*I, AMDGPU::OpName::vdst)->getReg();
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unsigned DestReg1
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= TII->getNamedOperand(*Paired, AMDGPU::OpName::vdst)->getReg();
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unsigned Offset0 = TII->getNamedOperand(*I, AMDGPU::OpName::offset)->getImm();
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unsigned Offset1
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= TII->getNamedOperand(*Paired, AMDGPU::OpName::offset)->getImm();
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const TargetRegisterClass *SuperRC
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= (EltSize == 4) ? &AMDGPU::VReg_64RegClass : &AMDGPU::VReg_128RegClass;
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unsigned DestReg = MRI->createVirtualRegister(SuperRC);
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DebugLoc DL = I->getDebugLoc();
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MachineInstrBuilder Read2
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= BuildMI(*MBB, I, DL, Read2InstDesc, DestReg)
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.addImm(0) // gds
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.addOperand(*AddrReg) // addr
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.addImm(Offset0 / EltSize) // offset0
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.addImm(Offset1 / EltSize) // offset1
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.addMemOperand(*I->memoperands_begin())
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.addMemOperand(*Paired->memoperands_begin());
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LIS->InsertMachineInstrInMaps(Read2);
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unsigned SubRegIdx0 = (EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
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unsigned SubRegIdx1 = (EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3;
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updateRegDefsUses(DestReg0, DestReg, SubRegIdx0);
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updateRegDefsUses(DestReg1, DestReg, SubRegIdx1);
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LIS->RemoveMachineInstrFromMaps(I);
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LIS->RemoveMachineInstrFromMaps(Paired);
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I->eraseFromParent();
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Paired->eraseFromParent();
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LiveInterval &AddrRegLI = LIS->getInterval(AddrReg->getReg());
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LIS->shrinkToUses(&AddrRegLI);
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LIS->getInterval(DestReg); // Create new LI
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DEBUG(dbgs() << "Inserted read2: " << *Read2 << '\n');
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return Read2;
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}
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MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair(
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
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unsigned EltSize,
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const MCInstrDesc &Write2InstDesc) {
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MachineBasicBlock *MBB = I->getParent();
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// Be sure to use .addOperand(), and not .addReg() with these. We want to be
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// sure we preserve the subregister index and any register flags set on them.
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const MachineOperand *Addr = TII->getNamedOperand(*I, AMDGPU::OpName::addr);
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const MachineOperand *Data0 = TII->getNamedOperand(*I, AMDGPU::OpName::data0);
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const MachineOperand *Data1
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= TII->getNamedOperand(*Paired, AMDGPU::OpName::data0);
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unsigned Offset0 = TII->getNamedOperand(*I, AMDGPU::OpName::offset)->getImm();
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unsigned Offset1
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= TII->getNamedOperand(*Paired, AMDGPU::OpName::offset)->getImm();
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DebugLoc DL = I->getDebugLoc();
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MachineInstrBuilder Write2
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= BuildMI(*MBB, I, DL, Write2InstDesc)
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.addImm(0) // gds
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.addOperand(*Addr) // addr
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.addOperand(*Data0) // data0
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.addOperand(*Data1) // data1
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.addImm(Offset0 / EltSize) // offset0
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.addImm(Offset1 / EltSize) // offset1
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.addMemOperand(*I->memoperands_begin())
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.addMemOperand(*Paired->memoperands_begin());
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// XXX - How do we express subregisters here?
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unsigned OrigRegs[] = { Data0->getReg(), Data1->getReg(), Addr->getReg() };
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LIS->RemoveMachineInstrFromMaps(I);
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LIS->RemoveMachineInstrFromMaps(Paired);
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I->eraseFromParent();
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Paired->eraseFromParent();
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LIS->repairIntervalsInRange(MBB, Write2, Write2, OrigRegs);
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DEBUG(dbgs() << "Inserted write2 inst: " << *Write2 << '\n');
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return Write2;
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}
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// Scan through looking for adjacent LDS operations with constant offsets from
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// the same base register. We rely on the scheduler to do the hard work of
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// clustering nearby loads, and assume these are all adjacent.
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bool SILoadStoreOptimizer::optimizeBlock(MachineBasicBlock &MBB) {
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const MCInstrDesc &Read2B32Desc = TII->get(AMDGPU::DS_READ2_B32);
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const MCInstrDesc &Read2B64Desc = TII->get(AMDGPU::DS_READ2_B64);
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const MCInstrDesc &Write2B32Desc = TII->get(AMDGPU::DS_WRITE2_B32);
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const MCInstrDesc &Write2B64Desc = TII->get(AMDGPU::DS_WRITE2_B64);
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bool Modified = false;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
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MachineInstr &MI = *I;
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// Don't combine if volatile.
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if (MI.hasOrderedMemoryRef()) {
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++I;
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continue;
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}
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unsigned Opc = MI.getOpcode();
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if (Opc == AMDGPU::DS_READ_B32 || Opc == AMDGPU::DS_READ_B64) {
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unsigned Size = (Opc == AMDGPU::DS_READ_B64) ? 8 : 4;
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MachineBasicBlock::iterator Match = findMatchingDSInst(I, Size);
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if (Match != E) {
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Modified = true;
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const MCInstrDesc &Read2Desc
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= (Opc == AMDGPU::DS_READ_B64) ? Read2B64Desc : Read2B32Desc;
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I = mergeRead2Pair(I, Match, Size, Read2Desc);
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} else {
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++I;
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}
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continue;
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} else if (Opc == AMDGPU::DS_WRITE_B32 || Opc == AMDGPU::DS_WRITE_B64) {
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unsigned Size = (Opc == AMDGPU::DS_WRITE_B64) ? 8 : 4;
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MachineBasicBlock::iterator Match = findMatchingDSInst(I, Size);
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if (Match != E) {
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Modified = true;
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const MCInstrDesc &Write2Desc
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= (Opc == AMDGPU::DS_WRITE_B64) ? Write2B64Desc : Write2B32Desc;
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I = mergeWrite2Pair(I, Match, Size, Write2Desc);
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} else {
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++I;
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}
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continue;
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}
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++I;
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}
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return Modified;
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}
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bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {
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const TargetSubtargetInfo *STM = MF.getTarget().getSubtargetImpl();
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TRI = static_cast<const SIRegisterInfo*>(STM->getRegisterInfo());
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TII = static_cast<const SIInstrInfo*>(STM->getInstrInfo());
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MRI = &MF.getRegInfo();
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LIS = &getAnalysis<LiveIntervals>();
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DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");
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assert(!MRI->isSSA());
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bool Modified = false;
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for (MachineBasicBlock &MBB : MF)
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Modified |= optimizeBlock(MBB);
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return Modified;
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}
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