llvm-6502/test/MC/Mips/octeon-instructions.s
Kai Nacke ebf9f0c6cb [MIPS] Add cpu octeon and some instructions
The Octeon cpu from Cavium Networks is mips64r2 based and has an extended
instruction set. In order to utilize this with LLVM, a new cpu feature "octeon"
and a subtarget feature "cnmips" is added. A small set of new instructions
(baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and
dpop instructions with option -mcpu=octeon or -mattr=+cnmips.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204337 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 11:51:58 +00:00

24 lines
1002 B
ArmAsm

# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=octeon | FileCheck %s
# CHECK: baddu $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x28]
# CHECK: baddu $17, $18, $19 # encoding: [0x72,0x53,0x88,0x28]
# CHECK: dmul $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x03]
# CHECK: dmul $19, $24, $25 # encoding: [0x73,0x19,0x98,0x03]
# CHECK: dpop $9, $6 # encoding: [0x70,0xc0,0x48,0x2d]
# CHECK: dpop $15, $22 # encoding: [0x72,0xc0,0x78,0x2d]
# CHECK: pop $9, $6 # encoding: [0x70,0xc0,0x48,0x2c]
# CHECK: pop $8, $19 # encoding: [0x72,0x60,0x40,0x2c]
# CHECK: seq $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2a]
# CHECK: sne $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2b]
baddu $9, $6, $7
baddu $17, $18, $19
dmul $9, $6, $7
dmul $19, $24, $25
dpop $9, $6
dpop $15, $22
pop $9, $6
pop $8, $19
seq $25, $23, $24
sne $25, $23, $24