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https://github.com/c64scene-ar/llvm-6502.git
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061efcfb3e
Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
2.7 KiB
C++
82 lines
2.7 KiB
C++
//===-- MBlazeTargetMachine.cpp - Define TargetMachine for MBlaze ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about MBlaze target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "MBlaze.h"
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#include "MBlazeTargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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extern "C" void LLVMInitializeMBlazeTarget() {
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// Register the target.
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RegisterTargetMachine<MBlazeTargetMachine> X(TheMBlazeTarget);
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}
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// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
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// The stack is always 8 byte aligned
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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// offset from the stack/frame pointer, using StackGrowsUp enables
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// an easier handling.
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MBlazeTargetMachine::
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MBlazeTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS),
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DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
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InstrInfo(*this),
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FrameLowering(Subtarget),
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TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this),
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InstrItins(Subtarget.getInstrItineraryData()) {
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}
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namespace {
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/// MBlaze Code Generator Pass Configuration Options.
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class MBlazePassConfig : public TargetPassConfig {
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public:
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MBlazePassConfig(MBlazeTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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MBlazeTargetMachine &getMBlazeTargetMachine() const {
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return getTM<MBlazeTargetMachine>();
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}
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virtual bool addInstSelector();
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virtual bool addPreEmitPass();
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};
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} // namespace
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TargetPassConfig *MBlazeTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new MBlazePassConfig(this, PM);
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}
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// Install an instruction selector pass using
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// the ISelDag to gen MBlaze code.
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bool MBlazePassConfig::addInstSelector() {
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PM.add(createMBlazeISelDag(getMBlazeTargetMachine()));
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return false;
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}
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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// print out the code after the passes.
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bool MBlazePassConfig::addPreEmitPass() {
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PM.add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
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return true;
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}
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