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https://github.com/c64scene-ar/llvm-6502.git
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543f70b040
Summary: This is similar to r210771 which did the same thing for MTHC1. Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the wrong definitions. Differential Revision: http://reviews.llvm.org/D4483 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212936 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
1.1 KiB
LLVM
41 lines
1.1 KiB
LLVM
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=NO-MFHC1 -check-prefix=ALL
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; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=NO-MFHC1 -check-prefix=ALL
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
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; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL
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@a = external global i32
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; ALL-LABEL: f:
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; NO-MFHC1: mtc1
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; NO-MFHC1: mtc1
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; HAS-MFHC1-DAG: mtc1
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; HAS-MFHC1-DAG: mthc1
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define double @f(i32 %a1, double %d) nounwind {
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entry:
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store i32 %a1, i32* @a, align 4
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%add = fadd double %d, 2.000000e+00
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ret double %add
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}
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; ALL-LABEL: f3:
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; NO-MFHC1: mfc1
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; NO-MFHC1: mfc1
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; HAS-MFHC1-DAG: mfc1
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; HAS-MFHC1-DAG: mfhc1
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define void @f3(double %d, i32 %a1) nounwind {
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entry:
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tail call void @f2(i32 %a1, double %d) nounwind
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ret void
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}
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declare void @f2(i32, double)
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