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https://github.com/c64scene-ar/llvm-6502.git
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14e97c4f51
Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210771 91177308-0d34-0410-b5e6-96231b3b80d8
364 lines
14 KiB
LLVM
364 lines
14 KiB
LLVM
; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are supported
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; correctly.
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; The spec for nmadd.[ds], and nmsub.[ds] does not state that they obey the
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; the Has2008 and ABS2008 configuration bits which govern the conformance to
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; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only
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; available when -enable-no-nans-fp-math is given.
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; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32 -check-prefix=32-NONAN
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NONAN
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; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NONAN
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64 -check-prefix=64-NONAN
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NONAN
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; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -mattr=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NONAN
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; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32 -check-prefix=32-NAN
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NAN
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; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NAN
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; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64 -check-prefix=64-NAN
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; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NAN
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; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -mattr=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NAN
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define float @FOO0float(float %a, float %b, float %c) nounwind readnone {
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entry:
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; ALL-LABEL: FOO0float:
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; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
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; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R2: add.s $f0, $[[T1]], $[[T2]]
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; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
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; 64-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
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; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 64-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
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; 64R2: add.s $f0, $[[T0]], $[[T1]]
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; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
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; 64R6-DAG: add.s $[[T1:f[0-9]+]], $[[T0]], $f14
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; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 64R6-DAG: add.s $f0, $[[T1]], $[[T2]]
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%mul = fmul float %a, %b
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%add = fadd float %mul, %c
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%add1 = fadd float %add, 0.000000e+00
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ret float %add1
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}
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define float @FOO1float(float %a, float %b, float %c) nounwind readnone {
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entry:
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; ALL-LABEL: FOO1float:
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; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
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; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R2: add.s $f0, $[[T1]], $[[T2]]
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; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32R6-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R6-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
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; 64-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
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; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 64-DAG: add.s $f0, $[[T1]], $[[T2]]
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; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
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; 64R2: add.s $f0, $[[T0]], $[[T1]]
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; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
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; 64R6-DAG: sub.s $[[T1:f[0-9]+]], $[[T0]], $f14
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; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 64R6-DAG: add.s $f0, $[[T1]], $[[T2]]
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%mul = fmul float %a, %b
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%sub = fsub float %mul, %c
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%add = fadd float %sub, 0.000000e+00
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ret float %add
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}
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define float @FOO2float(float %a, float %b, float %c) nounwind readnone {
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entry:
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; ALL-LABEL: FOO2float:
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; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32-DAG: sub.s $f0, $[[T2]], $[[T1]]
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; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R2-NONAN: nmadd.s $f0, $[[T0]], $f12, $f14
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; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
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; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
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; 32R6-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
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; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
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; 64-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
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; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 64-DAG: sub.s $f0, $[[T2]], $[[T1]]
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; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
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; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
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; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
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; 64R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
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; 64R6-DAG: add.s $[[T2:f[0-9]+]], $[[T1]], $f14
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; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 64R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
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%mul = fmul float %a, %b
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%add = fadd float %mul, %c
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%sub = fsub float 0.000000e+00, %add
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ret float %sub
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}
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define float @FOO3float(float %a, float %b, float %c) nounwind readnone {
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entry:
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; ALL-LABEL: FOO3float:
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; 32-DAG: mtc1 $6, $[[T0:f[0-9]+]]
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; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
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; 32-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32-DAG: sub.s $f0, $[[T2]], $[[T1]]
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; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R2-NONAN: nmsub.s $f0, $[[T0]], $f12, $f14
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; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
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; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
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; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
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; 64-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
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; 64-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
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; 64-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 64-DAG: sub.s $f0, $[[T2]], $[[T1]]
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; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
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; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
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; 64R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f13
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; 64R6-DAG: sub.s $[[T2:f[0-9]+]], $[[T1]], $f14
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; 64R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 64R6-DAG: sub.s $f0, $[[T2]], $[[T1]]
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%mul = fmul float %a, %b
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%sub = fsub float %mul, %c
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%sub1 = fsub float 0.000000e+00, %sub
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ret float %sub1
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}
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define double @FOO10double(double %a, double %b, double %c) nounwind readnone {
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entry:
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; ALL-LABEL: FOO10double:
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; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
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; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
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; 32-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32-DAG: add.d $f0, $[[T1]], $[[T2]]
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; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
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; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
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; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R2: mthc1 $zero, $[[T2]]
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; 32R2: add.d $f0, $[[T1]], $[[T2]]
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; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
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; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
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; 32R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]]
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; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
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; 64-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
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; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
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; 64-DAG: add.d $f0, $[[T1]], $[[T2]]
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; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
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; 64R2: add.d $f0, $[[T0]], $[[T1]]
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; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
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; 64R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
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; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
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; 64R6-DAG: add.d $f0, $[[T1]], $[[T2]]
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%mul = fmul double %a, %b
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%add = fadd double %mul, %c
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%add1 = fadd double %add, 0.000000e+00
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ret double %add1
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}
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define double @FOO11double(double %a, double %b, double %c) nounwind readnone {
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entry:
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; ALL-LABEL: FOO11double:
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; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
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; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
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; 32-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32-DAG: add.d $f0, $[[T1]], $[[T2]]
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; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
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; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
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; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R2: mthc1 $zero, $[[T2]]
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; 32R2: add.d $f0, $[[T1]], $[[T2]]
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; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
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; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
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; 32R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R6-DAG: add.d $f0, $[[T1]], $[[T2]]
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; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
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; 64-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
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; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
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; 64-DAG: add.d $f0, $[[T1]], $[[T2]]
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; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
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; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
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; 64R2: add.d $f0, $[[T0]], $[[T1]]
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; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
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; 64R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
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; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
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; 64R6-DAG: add.d $f0, $[[T1]], $[[T2]]
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%mul = fmul double %a, %b
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%sub = fsub double %mul, %c
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%add = fadd double %sub, 0.000000e+00
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ret double %add
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}
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define double @FOO12double(double %a, double %b, double %c) nounwind readnone {
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entry:
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; ALL-LABEL: FOO12double:
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; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
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; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
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; 32-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32-DAG: sub.d $f0, $[[T2]], $[[T1]]
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; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
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; 32R2-NONAN: nmadd.d $f0, $[[T0]], $f12, $f14
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; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
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; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
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; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
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; 32R2-NAN: mthc1 $zero, $[[T2]]
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; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
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|
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; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
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|
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
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; 32R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
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; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
|
; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
|
|
|
; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
|
|
; 64-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
|
|
; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
|
; 64-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
|
|
|
; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13
|
|
|
|
; 64R2-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
|
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
|
; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
|
|
|
|
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
|
|
; 64R6-DAG: add.d $[[T2:f[0-9]+]], $[[T1]], $f14
|
|
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
|
; 64R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
|
|
|
%mul = fmul double %a, %b
|
|
%add = fadd double %mul, %c
|
|
%sub = fsub double 0.000000e+00, %add
|
|
ret double %sub
|
|
}
|
|
|
|
define double @FOO13double(double %a, double %b, double %c) nounwind readnone {
|
|
entry:
|
|
; ALL-LABEL: FOO13double:
|
|
|
|
; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
|
; 32-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
|
; 32-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
|
; 32-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
|
; 32-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
|
|
|
; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
|
; 32R2-NONAN: nmsub.d $f0, $[[T0]], $f12, $f14
|
|
|
|
; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
|
; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
|
|
; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
|
|
; 32R2-NAN: mthc1 $zero, $[[T2]]
|
|
; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
|
|
|
|
; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
|
|
; 32R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f14
|
|
; 32R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $[[T0]]
|
|
; 32R6-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
|
|
; 32R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
|
|
|
; 64-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
|
|
; 64-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
|
|
; 64-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
|
; 64-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
|
|
|
; 64R2-NONAN: nmsub.d $f0, $f14, $f12, $f13
|
|
|
|
; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
|
|
; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
|
|
; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
|
|
|
|
; 64R6-DAG: mul.d $[[T1:f[0-9]+]], $f12, $f13
|
|
; 64R6-DAG: sub.d $[[T2:f[0-9]+]], $[[T1]], $f14
|
|
; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
|
; 64R6-DAG: sub.d $f0, $[[T2]], $[[T1]]
|
|
|
|
%mul = fmul double %a, %b
|
|
%sub = fsub double %mul, %c
|
|
%sub1 = fsub double 0.000000e+00, %sub
|
|
ret double %sub1
|
|
}
|