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https://github.com/c64scene-ar/llvm-6502.git
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d9accc1e5f
filler such as if delay slot filler have to put NOP instruction into the delay slot of microMIPS BEQ or BNE instruction which uses the register $0, then instead of emitting NOP this instruction is replaced by the corresponding microMIPS compact branch instruction, i.e. BEQZC or BNEZC. Differential Revision: http://reviews.llvm.org/D3566 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222580 91177308-0d34-0410-b5e6-96231b3b80d8
19 lines
562 B
LLVM
19 lines
562 B
LLVM
; RUN: llc %s -march=mipsel -mcpu=mips32r2 -mattr=micromips -filetype=asm \
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; RUN: -relocation-model=pic -o - | FileCheck %s
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@x = common global i32 0, align 4
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define i32 @AtomicLoadAdd32(i32 %incr) nounwind {
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entry:
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%0 = atomicrmw add i32* @x, i32 %incr monotonic
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ret i32 %0
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; CHECK-LABEL: AtomicLoadAdd32:
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; CHECK: lw $[[R0:[0-9]+]], %got(x)
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
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; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4
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; CHECK: sc $[[R2]], 0($[[R0]])
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; CHECK: beqzc $[[R2]], $[[BB0]]
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}
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