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https://github.com/c64scene-ar/llvm-6502.git
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c9ae6ee7a0
Fix bugs related to atomic microMIPS SC/LL instructions: While expanding atomic operations the mips32r2 encoding was emitted instead of microMIPS. Differential Revision: http://reviews.llvm.org/D6659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224524 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
1.2 KiB
LLVM
30 lines
1.2 KiB
LLVM
; RUN: llc -march=mipsel -filetype=obj --disable-machine-licm -mattr=micromips < %s -o - \
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; RUN: | llvm-objdump -no-show-raw-insn -arch mipsel -mcpu=mips32r2 -mattr=micromips -d - \
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; RUN: | FileCheck %s -check-prefix=MICROMIPS
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; Use llvm-objdump to check wheter the encodings of microMIPS atomic instructions are correct.
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; While emitting assembly files directly when in microMIPS mode, it is possible to emit a mips32r2
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; instruction instead of microMIPS instruction, and since many mips32r2 and microMIPS
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; instructions have identical assembly formats, invalid instruction cannot be detected.
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@y = common global i8 0, align 1
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define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
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entry:
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%0 = atomicrmw add i8* @y, i8 %incr monotonic
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ret i8 %0
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; MICROMIPS: ll ${{[0-9]+}}, 0(${{[0-9]+}})
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; MICROMIPS: sc ${{[0-9]+}}, 0(${{[0-9]+}})
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}
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define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
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entry:
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%pair0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic monotonic
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%0 = extractvalue { i8, i1 } %pair0, 0
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ret i8 %0
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; MICROMIPS: ll ${{[0-9]+}}, 0(${{[0-9]+}})
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; MICROMIPS: sc ${{[0-9]+}}, 0(${{[0-9]+}})
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}
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