mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-08 18:30:04 +00:00
0543dab791
Summary:
Two exceptions to this:
test/CodeGen/Mips/octeon.ll
test/CodeGen/Mips/octeon_popcnt.ll
these test extensions to MIPS64
One test is altered for MIPS-IV:
test/CodeGen/Mips/mips64countleading.ll
Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests
that dclo/dclz are not emitted.
Four tests fail and are not in this patch:
test/CodeGen/Mips/abicalls.ll
test/CodeGen/Mips/fcopysign-f32-f64.ll
test/CodeGen/Mips/fcopysign.ll
test/CodeGen/Mips/stack-alignment.ll
Depends on D3343
Reviewers: matheusalmeida, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3344
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206185 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
1.9 KiB
LLVM
61 lines
1.9 KiB
LLVM
; RUN: llc < %s -march=mips64el -mcpu=mips4 -mattr=-n64,n64 | FileCheck %s -check-prefix=CHECK-N64
|
|
; RUN: llc < %s -march=mips64el -mcpu=mips4 -mattr=-n64,n32 | FileCheck %s -check-prefix=CHECK-N32
|
|
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=-n64,n64 | FileCheck %s -check-prefix=CHECK-N64
|
|
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=-n64,n32 | FileCheck %s -check-prefix=CHECK-N32
|
|
|
|
@f0 = common global float 0.000000e+00, align 4
|
|
@d0 = common global double 0.000000e+00, align 8
|
|
@f1 = common global float 0.000000e+00, align 4
|
|
@d1 = common global double 0.000000e+00, align 8
|
|
|
|
define float @funcfl1() nounwind readonly {
|
|
entry:
|
|
; CHECK-N64: funcfl1
|
|
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0)
|
|
; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]])
|
|
; CHECK-N32: funcfl1
|
|
; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
|
|
; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]])
|
|
%0 = load float* @f0, align 4
|
|
ret float %0
|
|
}
|
|
|
|
define double @funcfl2() nounwind readonly {
|
|
entry:
|
|
; CHECK-N64: funcfl2
|
|
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0)
|
|
; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]])
|
|
; CHECK-N32: funcfl2
|
|
; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0)
|
|
; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]])
|
|
%0 = load double* @d0, align 8
|
|
ret double %0
|
|
}
|
|
|
|
define void @funcfs1() nounwind {
|
|
entry:
|
|
; CHECK-N64: funcfs1
|
|
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0)
|
|
; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]])
|
|
; CHECK-N32: funcfs1
|
|
; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
|
|
; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]])
|
|
%0 = load float* @f1, align 4
|
|
store float %0, float* @f0, align 4
|
|
ret void
|
|
}
|
|
|
|
define void @funcfs2() nounwind {
|
|
entry:
|
|
; CHECK-N64: funcfs2
|
|
; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0)
|
|
; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]])
|
|
; CHECK-N32: funcfs2
|
|
; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0)
|
|
; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]])
|
|
%0 = load double* @d1, align 8
|
|
store double %0, double* @d0, align 8
|
|
ret void
|
|
}
|
|
|