mirror of
https://github.com/c64scene-ar/llvm-6502.git
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38b2a0bfdd
Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210760 91177308-0d34-0410-b5e6-96231b3b80d8
80 lines
2.2 KiB
LLVM
80 lines
2.2 KiB
LLVM
; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC
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; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC
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; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR
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; FileCheck prefixes:
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; ALL - All targets
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; ACC - Targets with accumulator based mul/div (i.e. pre-MIPS32r6)
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; GPR - Targets with register based mul/div (i.e. MIPS32r6)
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define i64 @m0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: m0:
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; ACC: dmult ${{[45]}}, ${{[45]}}
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; ACC: mflo $2
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; GPR: dmul $2, ${{[45]}}, ${{[45]}}
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%mul = mul i64 %a1, %a0
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ret i64 %mul
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}
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define i64 @m1(i64 %a) nounwind readnone {
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entry:
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; ALL-LABEL: m1:
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; ALL: lui $[[T0:[0-9]+]], 21845
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; ALL: addiu $[[T0]], $[[T0]], 21845
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; ALL: dsll $[[T0]], $[[T0]], 16
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; ALL: addiu $[[T0]], $[[T0]], 21845
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; ALL: dsll $[[T0]], $[[T0]], 16
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; ALL: addiu $[[T0]], $[[T0]], 21846
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; ACC: dmult $4, $[[T0]]
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; ACC: mfhi $[[T1:[0-9]+]]
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; GPR: dmuh $[[T1:[0-9]+]], $4, $[[T0]]
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; ALL: dsrl $2, $[[T1]], 63
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; ALL: daddu $2, $[[T1]], $2
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%div = sdiv i64 %a, 3
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ret i64 %div
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}
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define i64 @d0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: d0:
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; ACC: ddivu $zero, $4, $5
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; ACC: mflo $2
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; GPR: ddivu $2, $4, $5
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%div = udiv i64 %a0, %a1
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ret i64 %div
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}
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define i64 @d1(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: d1:
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; ACC: ddiv $zero, $4, $5
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; ACC: mflo $2
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; GPR: ddiv $2, $4, $5
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%div = sdiv i64 %a0, %a1
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ret i64 %div
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}
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define i64 @d2(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: d2:
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; ACC: ddivu $zero, $4, $5
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; ACC: mfhi $2
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; GPR: dmodu $2, $4, $5
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%rem = urem i64 %a0, %a1
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ret i64 %rem
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}
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define i64 @d3(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: d3:
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; ACC: ddiv $zero, $4, $5
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; ACC: mfhi $2
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; GPR: dmod $2, $4, $5
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%rem = srem i64 %a0, %a1
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ret i64 %rem
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}
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