mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
ca795b61be
Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8
83 lines
2.7 KiB
LLVM
83 lines
2.7 KiB
LLVM
; Test the MSA fixed-point to floating point conversion intrinsics that are
|
|
; encoded with the 2RF instruction format.
|
|
|
|
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
|
|
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
|
|
|
@llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
|
|
@llvm_mips_ffql_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
|
|
|
|
define void @llvm_mips_ffql_w_test() nounwind {
|
|
entry:
|
|
%0 = load <8 x i16>* @llvm_mips_ffql_w_ARG1
|
|
%1 = tail call <4 x float> @llvm.mips.ffql.w(<8 x i16> %0)
|
|
store <4 x float> %1, <4 x float>* @llvm_mips_ffql_w_RES
|
|
ret void
|
|
}
|
|
|
|
declare <4 x float> @llvm.mips.ffql.w(<8 x i16>) nounwind
|
|
|
|
; CHECK: llvm_mips_ffql_w_test:
|
|
; CHECK: ld.h
|
|
; CHECK: ffql.w
|
|
; CHECK: st.w
|
|
; CHECK: .size llvm_mips_ffql_w_test
|
|
;
|
|
@llvm_mips_ffql_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
|
@llvm_mips_ffql_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
|
|
|
|
define void @llvm_mips_ffql_d_test() nounwind {
|
|
entry:
|
|
%0 = load <4 x i32>* @llvm_mips_ffql_d_ARG1
|
|
%1 = tail call <2 x double> @llvm.mips.ffql.d(<4 x i32> %0)
|
|
store <2 x double> %1, <2 x double>* @llvm_mips_ffql_d_RES
|
|
ret void
|
|
}
|
|
|
|
declare <2 x double> @llvm.mips.ffql.d(<4 x i32>) nounwind
|
|
|
|
; CHECK: llvm_mips_ffql_d_test:
|
|
; CHECK: ld.w
|
|
; CHECK: ffql.d
|
|
; CHECK: st.d
|
|
; CHECK: .size llvm_mips_ffql_d_test
|
|
;
|
|
@llvm_mips_ffqr_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
|
|
@llvm_mips_ffqr_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
|
|
|
|
define void @llvm_mips_ffqr_w_test() nounwind {
|
|
entry:
|
|
%0 = load <8 x i16>* @llvm_mips_ffqr_w_ARG1
|
|
%1 = tail call <4 x float> @llvm.mips.ffqr.w(<8 x i16> %0)
|
|
store <4 x float> %1, <4 x float>* @llvm_mips_ffqr_w_RES
|
|
ret void
|
|
}
|
|
|
|
declare <4 x float> @llvm.mips.ffqr.w(<8 x i16>) nounwind
|
|
|
|
; CHECK: llvm_mips_ffqr_w_test:
|
|
; CHECK: ld.h
|
|
; CHECK: ffqr.w
|
|
; CHECK: st.w
|
|
; CHECK: .size llvm_mips_ffqr_w_test
|
|
;
|
|
@llvm_mips_ffqr_d_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
|
@llvm_mips_ffqr_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
|
|
|
|
define void @llvm_mips_ffqr_d_test() nounwind {
|
|
entry:
|
|
%0 = load <4 x i32>* @llvm_mips_ffqr_d_ARG1
|
|
%1 = tail call <2 x double> @llvm.mips.ffqr.d(<4 x i32> %0)
|
|
store <2 x double> %1, <2 x double>* @llvm_mips_ffqr_d_RES
|
|
ret void
|
|
}
|
|
|
|
declare <2 x double> @llvm.mips.ffqr.d(<4 x i32>) nounwind
|
|
|
|
; CHECK: llvm_mips_ffqr_d_test:
|
|
; CHECK: ld.w
|
|
; CHECK: ffqr.d
|
|
; CHECK: st.d
|
|
; CHECK: .size llvm_mips_ffqr_d_test
|
|
;
|