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https://github.com/c64scene-ar/llvm-6502.git
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ca795b61be
Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
3.3 KiB
LLVM
95 lines
3.3 KiB
LLVM
; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction
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; format.
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; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
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@llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_mul_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_mul_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_mul_q_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_mul_q_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_mul_q_h_ARG2
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%2 = tail call <8 x i16> @llvm.mips.mul.q.h(<8 x i16> %0, <8 x i16> %1)
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store <8 x i16> %2, <8 x i16>* @llvm_mips_mul_q_h_RES
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ret void
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}
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declare <8 x i16> @llvm.mips.mul.q.h(<8 x i16>, <8 x i16>) nounwind
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; CHECK: llvm_mips_mul_q_h_test:
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: mul_q.h
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; CHECK: st.h
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; CHECK: .size llvm_mips_mul_q_h_test
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;
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@llvm_mips_mul_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_mul_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_mul_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_mul_q_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_mul_q_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_mul_q_w_ARG2
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%2 = tail call <4 x i32> @llvm.mips.mul.q.w(<4 x i32> %0, <4 x i32> %1)
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store <4 x i32> %2, <4 x i32>* @llvm_mips_mul_q_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.mul.q.w(<4 x i32>, <4 x i32>) nounwind
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; CHECK: llvm_mips_mul_q_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: mul_q.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_mul_q_w_test
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;
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@llvm_mips_mulr_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_mulr_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_mulr_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_mulr_q_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_mulr_q_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_mulr_q_h_ARG2
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%2 = tail call <8 x i16> @llvm.mips.mulr.q.h(<8 x i16> %0, <8 x i16> %1)
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store <8 x i16> %2, <8 x i16>* @llvm_mips_mulr_q_h_RES
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ret void
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}
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declare <8 x i16> @llvm.mips.mulr.q.h(<8 x i16>, <8 x i16>) nounwind
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; CHECK: llvm_mips_mulr_q_h_test:
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: mulr_q.h
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; CHECK: st.h
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; CHECK: .size llvm_mips_mulr_q_h_test
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;
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@llvm_mips_mulr_q_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_mulr_q_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_mulr_q_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_mulr_q_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_mulr_q_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_mulr_q_w_ARG2
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%2 = tail call <4 x i32> @llvm.mips.mulr.q.w(<4 x i32> %0, <4 x i32> %1)
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store <4 x i32> %2, <4 x i32>* @llvm_mips_mulr_q_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.mulr.q.w(<4 x i32>, <4 x i32>) nounwind
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; CHECK: llvm_mips_mulr_q_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: mulr_q.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_mulr_q_w_test
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;
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