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c5e99819f4
Hard float for mips16 means essentially to compile as soft float but to use a runtime library for soft float that is written with native mips32 floating point instructions (those runtime routines run in mips32 hard float mode). The patch reviewed by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195123 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1009 B
LLVM
46 lines
1009 B
LLVM
; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s -check-prefix=mips16
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; CHECK: rotrv $2, $4
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; mips16: .ent rot0
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define i32 @rot0(i32 %a, i32 %b) nounwind readnone {
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entry:
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%shl = shl i32 %a, %b
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%sub = sub i32 32, %b
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%shr = lshr i32 %a, %sub
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%or = or i32 %shr, %shl
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ret i32 %or
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}
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; CHECK: rotr $2, $4, 22
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; mips16: .ent rot1
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define i32 @rot1(i32 %a) nounwind readnone {
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entry:
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%shl = shl i32 %a, 10
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%shr = lshr i32 %a, 22
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%or = or i32 %shl, %shr
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ret i32 %or
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}
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; CHECK: rotrv $2, $4, $5
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; mips16: .ent rot2
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define i32 @rot2(i32 %a, i32 %b) nounwind readnone {
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entry:
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%shr = lshr i32 %a, %b
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%sub = sub i32 32, %b
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%shl = shl i32 %a, %sub
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%or = or i32 %shl, %shr
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ret i32 %or
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}
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; CHECK: rotr $2, $4, 10
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; mips16: .ent rot3
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define i32 @rot3(i32 %a) nounwind readnone {
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entry:
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%shr = lshr i32 %a, 10
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%shl = shl i32 %a, 22
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%or = or i32 %shr, %shl
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ret i32 %or
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}
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