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https://github.com/c64scene-ar/llvm-6502.git
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8007133f3e
Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210777 91177308-0d34-0410-b5e6-96231b3b80d8
44 lines
1.2 KiB
LLVM
44 lines
1.2 KiB
LLVM
; RUN: llc -march=mipsel -mcpu=mips32 < %s
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; RUN: llc -march=mipsel -mcpu=mips32 -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s
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; RUN: llc -march=mipsel -mcpu=mips32r2 -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED
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@gf0 = external global float
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@gf1 = external global float
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@gd0 = external global double
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@gd1 = external global double
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define float @select_cc_f32(float %a, float %b) nounwind {
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entry:
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; SOURCE-SCHED: lui
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; SOURCE-SCHED: addiu
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; SOURCE-SCHED: addu
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; SOURCE-SCHED: lw
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; SOURCE-SCHED: sw
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; SOURCE-SCHED: lw
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; SOURCE-SCHED: lui
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; SOURCE-SCHED: sw
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; SOURCE-SCHED: lw
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; SOURCE-SCHED: lwc1
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; SOURCE-SCHED: mtc1
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; SOURCE-SCHED: c.olt.s
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; SOURCE-SCHED: jr
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store float 0.000000e+00, float* @gf0, align 4
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store float 1.000000e+00, float* @gf1, align 4
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%cmp = fcmp olt float %a, %b
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%conv = zext i1 %cmp to i32
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%conv1 = sitofp i32 %conv to float
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ret float %conv1
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}
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define double @select_cc_f64(double %a, double %b) nounwind {
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entry:
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store double 0.000000e+00, double* @gd0, align 8
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store double 1.000000e+00, double* @gd1, align 8
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%cmp = fcmp olt double %a, %b
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%conv = zext i1 %cmp to i32
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%conv1 = sitofp i32 %conv to double
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ret double %conv1
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}
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