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0543dab791
Summary:
Two exceptions to this:
test/CodeGen/Mips/octeon.ll
test/CodeGen/Mips/octeon_popcnt.ll
these test extensions to MIPS64
One test is altered for MIPS-IV:
test/CodeGen/Mips/mips64countleading.ll
Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests
that dclo/dclz are not emitted.
Four tests fail and are not in this patch:
test/CodeGen/Mips/abicalls.ll
test/CodeGen/Mips/fcopysign-f32-f64.ll
test/CodeGen/Mips/fcopysign.ll
test/CodeGen/Mips/stack-alignment.ll
Depends on D3343
Reviewers: matheusalmeida, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3344
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206185 91177308-0d34-0410-b5e6-96231b3b80d8
54 lines
1.3 KiB
LLVM
54 lines
1.3 KiB
LLVM
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
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; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
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@gint_ = external global i32
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@gLL_ = external global i64
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; 32-LABEL: store_int_float_:
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; 32: trunc.w.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
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; 32: swc1 $f[[R0]],
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define void @store_int_float_(float %a) {
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entry:
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%conv = fptosi float %a to i32
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store i32 %conv, i32* @gint_, align 4
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ret void
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}
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; 32-LABEL: store_int_double_:
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; 32: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
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; 32: swc1 $f[[R0]],
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; 64-LABEL: store_int_double_:
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; 64: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
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; 64: swc1 $f[[R0]],
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define void @store_int_double_(double %a) {
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entry:
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%conv = fptosi double %a to i32
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store i32 %conv, i32* @gint_, align 4
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ret void
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}
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; 64-LABEL: store_LL_float_:
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; 64: trunc.l.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
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; 64: sdc1 $f[[R0]],
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define void @store_LL_float_(float %a) {
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entry:
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%conv = fptosi float %a to i64
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store i64 %conv, i64* @gLL_, align 8
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ret void
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}
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; 64-LABEL: store_LL_double_:
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; 64: trunc.l.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
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; 64: sdc1 $f[[R0]],
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define void @store_LL_double_(double %a) {
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entry:
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%conv = fptosi double %a to i64
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store i64 %conv, i64* @gLL_, align 8
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ret void
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}
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