llvm-6502/test/CodeGen/Mips/spill-copy-acreg.ll
Akira Hatanaka 99ad6ac65e [mips] Handle reading, writing or copying of ccond field of DSP control
register.

- Define pseudo instructions which store or load ccond field of the DSP
  control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-02 23:07:05 +00:00

42 lines
1.3 KiB
LLVM

; RUN: llc -march=mipsel -mattr=+dsp < %s
@g1 = common global i64 0, align 8
@g2 = common global i64 0, align 8
@g3 = common global i64 0, align 8
define i64 @test_acreg_copy(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
entry:
%0 = load i64* @g1, align 8
%1 = tail call i64 @llvm.mips.maddu(i64 %0, i32 %a0, i32 %a1)
%2 = tail call i64 @llvm.mips.maddu(i64 %0, i32 %a2, i32 %a3)
store i64 %1, i64* @g1, align 8
store i64 %2, i64* @g2, align 8
tail call void @foo1()
store i64 %2, i64* @g3, align 8
ret i64 %1
}
declare i64 @llvm.mips.maddu(i64, i32, i32)
declare void @foo1()
@g4 = common global <2 x i16> zeroinitializer, align 4
@g5 = common global <2 x i16> zeroinitializer, align 4
@g6 = common global <2 x i16> zeroinitializer, align 4
define { i32 } @test_ccond_spill(i32 %a.coerce, i32 %b.coerce) {
entry:
%0 = bitcast i32 %a.coerce to <2 x i16>
%1 = bitcast i32 %b.coerce to <2 x i16>
%cmp3 = icmp slt <2 x i16> %0, %1
%sext = sext <2 x i1> %cmp3 to <2 x i16>
store <2 x i16> %sext, <2 x i16>* @g4, align 4
tail call void @foo1()
%2 = load <2 x i16>* @g5, align 4
%3 = load <2 x i16>* @g6, align 4
%or = select <2 x i1> %cmp3, <2 x i16> %2, <2 x i16> %3
%4 = bitcast <2 x i16> %or to i32
%.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0
ret { i32 } %.fca.0.insert
}