mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 19:30:10 +00:00
972f5896e4
- Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37461 91177308-0d34-0410-b5e6-96231b3b80d8
520 lines
19 KiB
C++
520 lines
19 KiB
C++
//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Bruno Cardoso Lopes and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-lower"
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#include "MipsISelLowering.h"
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#include "MipsTargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/Debug.h"
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#include <queue>
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#include <set>
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using namespace llvm;
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const char *MipsTargetLowering::
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getTargetNodeName(unsigned Opcode) const
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{
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switch (Opcode)
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{
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case MipsISD::JmpLink : return "MipsISD::JmpLink";
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case MipsISD::Hi : return "MipsISD::Hi";
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case MipsISD::Lo : return "MipsISD::Lo";
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case MipsISD::Ret : return "MipsISD::Ret";
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default : return NULL;
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}
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}
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MipsTargetLowering::
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MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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{
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// Mips does not have i1 type, so use i32 for
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// setcc operations results (slt, sgt, ...).
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setSetCCResultType(MVT::i32);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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// Set up the register classes
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addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
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// Custom
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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// Load extented operations for i1 types must be promoted
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setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
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// Store operations for i1 types must be promoted
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setStoreXAction(MVT::i1, Promote);
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// Mips does not have these NodeTypes below.
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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// Mips not supported intrinsics.
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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setOperationAction(ISD::MEMSET, MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ , MVT::i32, Expand);
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setOperationAction(ISD::CTLZ , MVT::i32, Expand);
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setOperationAction(ISD::ROTL , MVT::i32, Expand);
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setOperationAction(ISD::ROTR , MVT::i32, Expand);
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::LABEL, MVT::Other, Expand);
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// Use the default for now
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setStackPointerRegisterToSaveRestore(Mips::SP);
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computeRegisterProperties();
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}
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SDOperand MipsTargetLowering::
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LowerOperation(SDOperand Op, SelectionDAG &DAG)
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{
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switch (Op.getOpcode())
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{
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case ISD::CALL: return LowerCALL(Op, DAG);
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
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}
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return SDOperand();
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}
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//===----------------------------------------------------------------------===//
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// Lower helper functions
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//===----------------------------------------------------------------------===//
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// AddLiveIn - This helper function adds the specified physical register to the
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// MachineFunction as a live in value. It also creates a corresponding
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// virtual register for it.
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static unsigned
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AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
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{
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assert(RC->contains(PReg) && "Not the correct regclass!");
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unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
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MF.addLiveIn(PReg, VReg);
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return VReg;
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}
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// Set up a frame object for the return address.
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SDOperand MipsTargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
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if (ReturnAddrIndex == 0) {
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MachineFunction &MF = DAG.getMachineFunction();
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ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, 0);
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}
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return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
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}
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//===----------------------------------------------------------------------===//
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// Misc Lower Operation implementation
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//===----------------------------------------------------------------------===//
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SDOperand MipsTargetLowering::
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LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG)
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{
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GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
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SDOperand Hi = DAG.getNode(MipsISD::Hi, MVT::i32, GA);
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SDOperand Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
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return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
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}
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SDOperand MipsTargetLowering::
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LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
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// Depths > 0 not supported yet!
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if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
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return SDOperand();
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// Just load the return address
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SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
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return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//
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// The lower operations present on calling convention works on this order:
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// LowerCALL (virt regs --> phys regs, virt regs --> stack)
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// LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
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// LowerRET (virt regs --> phys regs)
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// LowerCALL (phys regs --> virt regs)
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//
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//===----------------------------------------------------------------------===//
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#include "MipsGenCallingConv.inc"
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//===----------------------------------------------------------------------===//
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// CALL Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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/// Mips custom CALL implementation
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SDOperand MipsTargetLowering::
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LowerCALL(SDOperand Op, SelectionDAG &DAG)
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{
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unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
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// By now, only CallingConv::C implemented
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switch (CallingConv)
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{
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default:
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assert(0 && "Unsupported calling convention");
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case CallingConv::Fast:
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case CallingConv::C:
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return LowerCCCCallTo(Op, DAG, CallingConv);
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}
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}
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/// LowerCCCCallTo - functions arguments are copied from virtual
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/// regs to (physical regs)/(stack frame), CALLSEQ_START and
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/// CALLSEQ_END are emitted.
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/// TODO: isVarArg, isTailCall, sret, GOT, linkage types.
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SDOperand MipsTargetLowering::
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LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
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{
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SDOperand Chain = Op.getOperand(0);
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SDOperand Callee = Op.getOperand(4);
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CC, getTargetMachine(), ArgLocs);
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CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
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getPointerTy()));
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SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
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SmallVector<SDOperand, 8> MemOpChains;
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SDOperand StackPtr;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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// Arguments start after the 5 first operands of ISD::CALL
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SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default: assert(0 && "Unknown loc info!");
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
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break;
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}
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// Arguments that can be passed on register,
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// must be kept at RegsToPass vector
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else {
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assert(VA.isMemLoc());
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// Mips::SP holds our stack pointer
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if (StackPtr.Val == 0)
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StackPtr = DAG.getRegister(Mips::SP, getPointerTy());
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SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(),
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getPointerTy());
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// emit a ISD::ADD which emits the final
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// stack location to place the parameter
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PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
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// emit ISD::STORE whichs stores the
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// parameter value to a stack Location
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MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
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}
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}
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// Transform all store nodes into one single node because
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// all store nodes ar independent of each other.
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes chained together with token
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// chain and flag operands which copy the outgoing args into registers.
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// The InFlag in necessary since all emited instructions must be
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// stuck together.
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SDOperand InFlag;
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
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RegsToPass[i].second, InFlag);
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InFlag = Chain.getValue(1);
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}
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// If the callee is a GlobalAddress node (quite common, every direct
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// call is) turn it into a TargetGlobalAddress node so that legalize
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// doesn't hack it.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
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} else
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if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
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// MipsJmpLink = #chain, #target_address, #opt_in_flags...
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// = Chain, Callee, Reg#1, Reg#2, ...
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//
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// Returns a chain & a flag for retval copy to use.
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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SmallVector<SDOperand, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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// Add argument registers to the end of the list so that they are
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// known live into the call.
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
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Ops.push_back(DAG.getRegister(RegsToPass[i].first,
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RegsToPass[i].second.getValueType()));
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if (InFlag.Val)
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Ops.push_back(InFlag);
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Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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// Create the CALLSEQ_END node.
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NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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Ops.clear();
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Ops.push_back(Chain);
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Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
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Ops.push_back(InFlag);
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Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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// Handle result values, copying them out of physregs into vregs that we
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// return.
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return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
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}
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/// LowerCallResult - Lower the result values of an ISD::CALL into the
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/// appropriate copies out of appropriate physical registers. This assumes that
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/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
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/// being lowered. Returns a SDNode with the same number of values as the
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/// ISD::CALL.
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SDNode *MipsTargetLowering::
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LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
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unsigned CallingConv, SelectionDAG &DAG) {
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallingConv, getTargetMachine(), RVLocs);
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CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
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SmallVector<SDOperand, 8> ResultVals;
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// returns void
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if (!RVLocs.size())
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return Chain.Val;
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
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RVLocs[i].getValVT(), InFlag).getValue(1);
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InFlag = Chain.getValue(2);
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ResultVals.push_back(Chain.getValue(0));
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}
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// Merge everything together with a MERGE_VALUES node.
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ResultVals.push_back(Chain);
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return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
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&ResultVals[0], ResultVals.size()).Val;
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}
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//===----------------------------------------------------------------------===//
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// FORMAL_ARGUMENTS Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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/// Mips custom FORMAL_ARGUMENTS implementation
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SDOperand MipsTargetLowering::
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LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG)
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{
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unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
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switch(CC)
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{
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default:
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assert(0 && "Unsupported calling convention");
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case CallingConv::C:
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return LowerCCCArguments(Op, DAG);
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}
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}
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/// LowerCCCArguments - transform physical registers into
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/// virtual registers and generate load operations for
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/// arguments places on the stack.
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/// TODO: isVarArg, sret
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SDOperand MipsTargetLowering::
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LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
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{
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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SDOperand Root = Op.getOperand(0);
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(MF.getFunction()->getCallingConv(),
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getTargetMachine(), ArgLocs);
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CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
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SmallVector<SDOperand, 8> ArgValues;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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// Arguments stored on registers
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if (VA.isRegLoc()) {
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MVT::ValueType RegVT = VA.getLocVT();
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TargetRegisterClass *RC;
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if (RegVT == MVT::i32)
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RC = Mips::CPURegsRegisterClass;
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else
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assert(0 && "support only Mips::CPURegsRegisterClass");
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unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
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// Transform the arguments stored on
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// physical registers into virtual ones
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SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
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// If this is an 8 or 16-bit value, it is really passed promoted
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// to 32 bits. Insert an assert[sz]ext to capture this, then
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// truncate to the right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
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ArgValues.push_back(ArgValue);
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} else {
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// sanity check
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assert(VA.isMemLoc());
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
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VA.getLocMemOffset());
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// Create load nodes to retrieve arguments from the stack
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SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
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ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
|
|
}
|
|
}
|
|
ArgValues.push_back(Root);
|
|
|
|
ReturnAddrIndex = 0;
|
|
|
|
// Return the new list of results.
|
|
return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
|
|
&ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Return Value Calling Convention Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
SDOperand MipsTargetLowering::
|
|
LowerRET(SDOperand Op, SelectionDAG &DAG)
|
|
{
|
|
// CCValAssign - represent the assignment of
|
|
// the return value to a location
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
|
|
|
|
// CCState - Info about the registers and stack slot.
|
|
CCState CCInfo(CC, getTargetMachine(), RVLocs);
|
|
|
|
// Analize return values of ISD::RET
|
|
CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
|
|
|
|
// If this is the first return lowered for this function, add
|
|
// the regs to the liveout set for the function.
|
|
if (DAG.getMachineFunction().liveout_empty()) {
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i)
|
|
DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
|
|
}
|
|
|
|
// The chain is always operand #0
|
|
SDOperand Chain = Op.getOperand(0);
|
|
SDOperand Flag;
|
|
|
|
// Copy the result values into the output registers.
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
CCValAssign &VA = RVLocs[i];
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
|
|
// ISD::RET => ret chain, (regnum1,val1), ...
|
|
// So i*2+1 index only the regnums
|
|
Chain = DAG.getCopyToReg(Chain, VA.getLocReg(),
|
|
Op.getOperand(i*2+1), Flag);
|
|
|
|
// guarantee that all emitted copies are
|
|
// stuck together, avoiding something bad
|
|
Flag = Chain.getValue(1);
|
|
}
|
|
|
|
// Return on Mips is always a "jr $ra"
|
|
if (Flag.Val)
|
|
return DAG.getNode(MipsISD::Ret, MVT::Other,
|
|
Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
|
|
else // Return Void
|
|
return DAG.getNode(MipsISD::Ret, MVT::Other,
|
|
Chain, DAG.getRegister(Mips::RA, MVT::i32));
|
|
}
|