llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-21 19:32:16 +00:00

History

Moritz Roth 9753aab704 ARM load/store optimizer: Don't materialize a new base register with

ADDS/SUBS unless it's safe to clobber the condition flags.

If the merged instructions are in a range where the CPSR is live,
e.g. between a CMP -> Bcc, we can't safely materialize a new base
register.

This problem is quite rare, I couldn't come up with a test case and I've
never actually seen this happen in the tests I'm running - there is a
potential trigger for this in LNT/oggenc (spills being inserted between
a CMP/Bcc), but at the moment this isn't being merged. I'll try to
reduce that into a small test case once I've committed my upcoming patch
to make merging less conservative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217881 91177308-0d34-0410-b5e6-96231b3b80d8

2014-09-16 16:25:07 +00:00

Analysis

InstSimplify: Simplify trivial and/or of icmps

2014-09-15 08:15:28 +00:00

AsmParser

…

Bitcode

Use IntrusiveRefCntPtr to manage the lifetime of BitCodeAbbrevs.

2014-09-15 15:44:14 +00:00

CodeGen

Fix BasicTTI::getCmpSelInstrCost to deal with illegal vector types

2014-09-16 04:35:50 +00:00