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https://github.com/c64scene-ar/llvm-6502.git
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84a2c2bbb5
This patch doesn't introduce any functionality changes. It adds some new fields to the Hexagon instruction classes and changes their layout to support instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175205 91177308-0d34-0410-b5e6-96231b3b80d8
67 lines
2.5 KiB
TableGen
67 lines
2.5 KiB
TableGen
//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon V4 instruction classes in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//----------------------------------------------------------------------------//
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// Hexagon Intruction Flags +
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//
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// *** Must match BaseInfo.h ***
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//----------------------------------------------------------------------------//
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def TypeMEMOP : IType<9>;
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def TypeNV : IType<10>;
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def TypePREFIX : IType<30>;
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//----------------------------------------------------------------------------//
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// Intruction Classes Definitions +
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//----------------------------------------------------------------------------//
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//
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// NV type instructions.
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//
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class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4, TypeNV>;
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class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: NVInst<outs, ins, asmstr, pattern, cstr>;
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// Definition of Post increment new value store.
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class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: NVInst<outs, ins, asmstr, pattern, cstr>;
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// Post increment ST Instruction.
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let mayStore = 1 in
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class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: NVInst<outs, ins, asmstr, pattern, cstr>;
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// New-value conditional branch.
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class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: NVInst<outs, ins, asmstr, pattern, cstr>;
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let mayLoad = 1, mayStore = 1 in
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class MEMInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, MEM_V4, TypeMEMOP>;
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class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: MEMInst<outs, ins, asmstr, pattern, cstr>;
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let isCodeGenOnly = 1 in
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class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX>;
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