Nadav Rotem 0509db2738 AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171178 91177308-0d34-0410-b5e6-96231b3b80d8		2012-12-28 05:45:24 +00:00
..
ARM	Revert "Adding support for llvm.arm.neon.vaddl[su].* and"	2012-12-20 21:09:38 +00:00
CPP
Generic	After reducing the size of an operation in the DAG we zero-extend the reduced	2012-12-19 07:39:08 +00:00
Hexagon	In hexagon convertToHardwareLoop, don't deref end() iterator	2012-12-07 21:03:15 +00:00
MBlaze
Mips	Add test case for r170674	2012-12-21 00:55:10 +00:00
MSP430
NVPTX
PowerPC	Loosen scheduling restrictions on the PPC dcbt intrinsic	2012-12-25 18:51:18 +00:00
R600	R600: Expand vec4 INT <-> FP conversions	2012-12-21 16:33:24 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC
Thumb
Thumb2	On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,	2012-12-20 19:59:30 +00:00
X86	AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend.	2012-12-28 05:45:24 +00:00
XCore