mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 19:30:10 +00:00
97b2a2e389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15751 91177308-0d34-0410-b5e6-96231b3b80d8
202 lines
8.1 KiB
TableGen
202 lines
8.1 KiB
TableGen
//===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the subset of the 32-bit PowerPC instruction set, as used
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// by the PowerPC instruction selector.
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//
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//===----------------------------------------------------------------------===//
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include "PowerPCInstrFormats.td"
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let isTerminator = 1, isReturn = 1 in
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def BLR : XLForm_2_ext<"blr", 19, 16, 20, 31, 1, 0, 0>;
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class II<dag OL, string asmstr> {
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dag OperandList = OL;
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string AsmString = asmstr;
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}
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def u16imm : Operand<i16> {
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let PrintMethod = "printU16ImmOperand";
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}
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// Pseudo-instructions:
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def PHI : Pseudo<"PHI">; // PHI node...
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def ADJCALLSTACKDOWN : Pseudo<"ADJCALLSTACKDOWN">;
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def ADJCALLSTACKUP : Pseudo<"ADJCALLSTACKUP">;
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let Defs = [LR] in
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def MovePCtoLR : Pseudo<"MovePCtoLR">;
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def IMPLICIT_DEF : Pseudo<"IMPLICIT_DEF">;
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def LOADLoIndirect : DForm_2_r0 <"lwz", 14, 0, 0>;
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def LOADLoDirect : DForm_2_r0<"la", 14, 0, 0>;
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def LOADHiAddr : DForm_2_r0<"addis", 15, 0, 0>;
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def ADDI : DForm_2<"addi", 14, 0, 0>;
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def ADDIS : DForm_2<"addis", 15, 0, 0>;
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def SUBI : DForm_2<"subi", 14, 0, 0>;
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def LI : DForm_2_r0<"li", 14, 0, 0>;
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def LIS : DForm_2_r0<"lis", 15, 0, 0>;
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def ADDIC : DForm_2<"addic", 12, 0, 0>;
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def ADD : XOForm_1<"add", 31, 266, 0, 0, 0, 0>;
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def ADDC : XOForm_1<"addc", 31, 10, 0, 0, 0, 0>;
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def ADDE : XOForm_1<"adde", 31, 138, 0, 0, 0, 0>;
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def ADDZE : XOForm_3<"addze", 31, 202, 0, 0, 0, 0>;
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def ANDIo : DForm_4<28, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"andi. $dst, $src1, $src2">;
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def AND : XForm_6<"and", 31, 28, 0, 0, 0>;
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def ANDC : XForm_6<"andc", 31, 60, 0, 0, 0>;
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let isBranch = 1, isTerminator = 1 in {
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def COND_BRANCH : Pseudo<"COND_BRANCH">;
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def B : IForm<"b", 18, 0, 0, 0, 0>;
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// FIXME: 4*CR# needs to be added to the BI field!
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// This will only work for CR0 as it stands now
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def BLT : BForm_ext<"blt", 16, 0, 0, 12, 0, 0, 0>;
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def BLE : BForm_ext<"ble", 16, 0, 0, 4, 1, 0, 0>;
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def BEQ : BForm_ext<"beq", 16, 0, 0, 12, 2, 0, 0>;
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def BGE : BForm_ext<"bge", 16, 0, 0, 4, 0, 0, 0>;
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def BGT : BForm_ext<"bgt", 16, 0, 0, 12, 1, 0, 0>;
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def BNE : BForm_ext<"bne", 16, 0, 0, 4, 2, 0, 0>;
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}
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let isBranch = 1, isTerminator = 1, isCall = 1,
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// All calls clobber the non-callee saved registers...
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Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
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F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
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LR,XER,CTR,
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CR0,CR1,CR5,CR6,CR7] in {
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// Convenient aliases for call instructions
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def CALLpcrel : IForm<"bl", 18, 0, 1, 0, 0>;
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def CALLindirect : XLForm_2_ext<"bctrl", 19, 528, 20, 31, 1, 0, 0>;
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}
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def CMPI : DForm_5<"cmpi", 11, 0, 0>;
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def CMPWI : DForm_5_ext<"cmpwi", 11, 0, 0>;
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def CMPDI : DForm_5_ext<"cmpdi", 11, 1, 0>;
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def CMP : XForm_16<"cmp", 31, 0, 0, 0>;
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def CMPW : XForm_16_ext<"cmpw", 31, 0, 0, 0>;
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def CMPD : XForm_16_ext<"cmpd", 31, 0, 1, 0>;
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def CMPLI : DForm_6<"cmpli", 10, 0, 0>;
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def CMPLWI : DForm_6_ext<"cmplwi", 10, 0, 0>;
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def CMPLDI : DForm_6_ext<"cmpldi", 10, 1, 0>;
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def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>;
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def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>;
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def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>;
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def CRAND : XLForm_1<"crand", 19, 257, 0, 0>;
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def CRANDC : XLForm_1<"crandc", 19, 129, 0, 0>;
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def CRNOR : XLForm_1<"crnor", 19, 33, 0, 0>;
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def CROR : XLForm_1<"cror", 19, 449, 0, 0>;
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def DIVW : XOForm_1<"divw", 31, 491, 0, 0, 0, 0>;
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def DIVWU : XOForm_1<"divwu", 31, 459, 0, 0, 0, 0>;
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def EXTSB : XForm_11<"extsb", 31, 954, 0, 0, 0>;
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def EXTSH : XForm_11<"extsh", 31, 922, 0, 0, 0>;
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def FADD : AForm_2<"fadd", 63, 21, 0, 0, 0>;
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def FADDS : AForm_2<"fadds", 59, 21, 0, 0, 0>;
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def FSUB : AForm_2<"fsub", 63, 20, 0, 0, 0>;
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def FSUBS : AForm_2<"fsubs", 59, 20, 0, 0, 0>;
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def FMUL : AForm_3<"fmul", 63, 25, 0, 0, 0>;
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def FMULS : AForm_3<"fmuls", 59, 25, 0, 0, 0>;
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def FDIV : AForm_2<"fdiv", 63, 18, 0, 0, 0>;
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def FDIVS : AForm_2<"fdivs", 59, 18, 0, 0, 0>;
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def FMR : XForm_26<"fmr", 63, 72, 0, 0, 0>;
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def FNEG : XForm_26<"fneg", 63, 80, 0, 0, 0>;
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def FRSP : XForm_26<"frsp", 63, 12, 0, 0, 0>;
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def FSEL : AForm_1<"fsel", 63, 23, 0, 0, 0>;
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def FCTIW : XForm_26<"fctiw", 63, 14, 0, 0, 0>;
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def FCTIWZ : XForm_26<"fctiwz", 63, 15, 0, 0, 0>;
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def FCMPU : XForm_17<"fcmpu", 63, 0, 0, 0>;
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def LBZ : DForm_1<"lbz", 35, 0, 0>;
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def LBZX : XForm_1<"lbzx", 31, 87, 0, 0>;
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def LHZ : DForm_1<"lhz", 40, 0, 0>;
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def LHZX : XForm_1<"lhzx", 31, 279, 0, 0>;
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def LHA : DForm_1<"lha", 42, 0, 0>;
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def LHAX : XForm_1<"lhax", 31, 343, 0, 0>;
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def LWZ : DForm_1<"lwz", 32, 0, 0>;
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def LWZX : XForm_1<"lwzx", 31, 23, 0, 0>;
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def LWA : DSForm_1<"lwa", 58, 2, 1, 0>;
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def LWAX : XForm_1<"lwax", 31, 341, 1, 0>;
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def LD : DSForm_2<"ld", 58, 0, 1, 0>;
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def LDX : XForm_1<"ldx", 31, 21, 1, 0>;
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def LMW : DForm_1<"lmw", 46, 0, 0>;
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def STMW : DForm_3<"stmw", 47, 0, 0>;
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def LFS : DForm_8<"lfs", 48, 0, 0>;
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def LFSX : XForm_25<"lfsx", 31, 535, 0, 0>;
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def LFD : DForm_8<"lfd", 50, 0, 0>;
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def LFDX : XForm_25<"lfdx", 31, 599, 0, 0>;
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def MFCR : XForm_5<"mfcr", 31, 19, 0, 0>;
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def MFLR : XFXForm_1_ext<"", 31, 399, 8, 0, 0>,
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II<(ops GPRC:$reg), "mflr $reg">;
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def MFCTR : XFXForm_1_ext<"mfctr", 31, 399, 9, 0, 0>;
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def MTLR : XFXForm_7_ext<"mtlr", 31, 467, 8, 0, 0>;
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def MTCTR : XFXForm_7_ext<"mtctr", 31, 467, 9, 0, 0>;
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def MULLD : XOForm_1<"mulld", 31, 233, 0, 0, 1, 0>;
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def MULLW : XOForm_1<"mullw", 31, 235, 0, 0, 0, 0>;
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def MULHWU : XOForm_2<"mulhwu", 31, 11, 0, 0, 0>;
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def NAND : XForm_6<"nand", 31, 476, 0, 0, 0>;
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def NEG : XOForm_3<"neg", 31, 104, 0, 0, 0, 0>;
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def NOR : XForm_6<"nor", 31, 124, 0, 0, 0>;
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def NOP : DForm_4_zero<"nop", 24, 0, 0>;
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def ORI : DForm_4<24, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2">;
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def ORIS : DForm_4<25, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"oris $dst, $src1, $src2">;
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def OR : XForm_6<"or", 31, 444, 0, 0, 0>;
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def ORo : XForm_6<"or.", 31, 444, 1, 0, 0>;
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def RLDICL : MDForm_1<"rldicl", 30, 0, 0, 1, 0>;
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def RLDICR : MDForm_1<"rldicr", 30, 1, 0, 1, 0>;
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def RLWINM : MForm_2<"rlwinm", 21, 0, 0, 0>;
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def RLWNM : MForm_1<"rlwnm", 23, 0, 0, 0>;
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def RLWIMI : MForm_2<"rlwimi", 20, 0, 0, 0>;
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def SLD : XForm_6<"sld", 31, 27, 0, 1, 0>;
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def SLW : XForm_6<"slw", 31, 24, 0, 0, 0>;
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def SRD : XForm_6<"srd", 31, 539, 0, 1, 0>;
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def SRW : XForm_6<"srw", 31, 536, 0, 0, 0>;
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def SRADI : XSForm_1<"sradi", 31, 413, 0, 1, 0>;
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def SRAWI : XForm_10<"srawi", 31, 824, 0, 0, 0>;
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def SRAD : XForm_6<"srad", 31, 794, 0, 1, 0>;
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def SRAW : XForm_6<"sraw", 31, 792, 0, 0, 0>;
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def STB : DForm_3<"stb", 38, 0, 0>;
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def STBU : DForm_3<"stbu", 39, 0, 0>;
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def STBX : XForm_8<"stbx", 31, 215, 0, 0>;
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def STH : DForm_3<"sth", 44, 0, 0>;
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def STHU : DForm_3<"sthu", 45, 0, 0>;
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def STHX : XForm_8<"sthx", 31, 407, 0, 0>;
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def STW : DForm_3<"stw", 36, 0, 0>;
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def STWU : DForm_3<"stwu", 37, 0, 0>;
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def STWX : XForm_8<"stwx", 31, 151, 0, 0>;
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def STWUX : XForm_8<"stwux", 31, 183, 0, 0>;
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def STD : DSForm_2<"std", 62, 0, 1, 0>;
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def STDU : DSForm_2<"stdu", 62, 1, 1, 0>;
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def STDX : XForm_8<"stdx", 31, 149, 1, 0>;
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def STDUX : XForm_8<"stdux", 31, 181, 1, 0>;
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def STFS : DForm_9<"stfs", 52, 0, 0>;
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def STFSX : XForm_28<"stfsx", 31, 663, 0, 0>;
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def STFD : DForm_9<"stfd", 54, 0, 0>;
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def STFDX : XForm_28<"stfdx", 31, 727, 0, 0>;
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def SUBFIC : DForm_2<"subfic", 8, 0, 0>;
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def SUB : XOForm_1_rev<"sub", 31, 40, 0, 0, 0, 0>;
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def SUBF : XOForm_1<"subf", 31, 40, 0, 0, 0, 0>;
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def SUBC : XOForm_1_rev<"subc", 31, 8, 0, 0, 0, 0>;
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def SUBFC : XOForm_1<"subfc", 31, 8, 0, 0, 0, 0>;
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def SUBFE : XOForm_1<"subfe", 31, 136, 0, 0, 0, 0>;
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def SUBFZE : XOForm_3<"subfze", 31, 200, 0, 0, 0, 0>;
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def XORI : DForm_4<26, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"xori $dst, $src1, $src2">;
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def XORIS : DForm_4<27, 0, 0,
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(ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
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"xoris $dst, $src1, $src2">;
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def XOR : XForm_6<"xor", 31, 316, 0, 0, 0>;
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def MULLI : DForm_2<"mulli", 7, 0, 0>;
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