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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153844 91177308-0d34-0410-b5e6-96231b3b80d8
617 lines
33 KiB
TableGen
617 lines
33 KiB
TableGen
//===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Primary reference:
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// PowerPC 440x6 Embedded Processor Core User's Manual.
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// IBM (as updated in) 2010.
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// The basic PPC 440 does not include a floating-point unit; the pipeline
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// timings here are constructed to match the FP2 unit shipped with the
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// PPC-440- and PPC-450-based Blue Gene (L and P) supercomputers.
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// References:
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// S. Chatterjee, et al. Design and exploitation of a high-performance
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// SIMD floating-point unit for Blue Gene/L.
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// IBM J. Res. & Dev. 49 (2/3) March/May 2005.
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// also:
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// Carlos Sosa and Brant Knudson. IBM System Blue Gene Solution:
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// Blue Gene/P Application Development.
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// IBM (as updated in) 2009.
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//===----------------------------------------------------------------------===//
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// Functional units on the PowerPC 440/450 chip sets
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//
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def IFTH1 : FuncUnit; // Fetch unit 1
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def IFTH2 : FuncUnit; // Fetch unit 2
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def PDCD1 : FuncUnit; // Decode unit 1
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def PDCD2 : FuncUnit; // Decode unit 2
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def DISS1 : FuncUnit; // Issue unit 1
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def DISS2 : FuncUnit; // Issue unit 2
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def LRACC : FuncUnit; // Register access and dispatch for
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// the simple integer (J-pipe) and
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// load/store (L-pipe) pipelines
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def IRACC : FuncUnit; // Register access and dispatch for
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// the complex integer (I-pipe) pipeline
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def FRACC : FuncUnit; // Register access and dispatch for
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// the floating-point execution (F-pipe) pipeline
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def IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline
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def IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline
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def IWB : FuncUnit; // Write-back unit for the I pipeline
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def JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline
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def JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline
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def JWB : FuncUnit; // Write-back unit for the J pipeline
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def AGEN : FuncUnit; // Address generation for the L pipeline
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def CRD : FuncUnit; // D-cache access for the L pipeline
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def LWB : FuncUnit; // Write-back unit for the L pipeline
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def FEXE1 : FuncUnit; // Execution stage 1 for the F pipeline
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def FEXE2 : FuncUnit; // Execution stage 2 for the F pipeline
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def FEXE3 : FuncUnit; // Execution stage 3 for the F pipeline
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def FEXE4 : FuncUnit; // Execution stage 4 for the F pipeline
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def FEXE5 : FuncUnit; // Execution stage 5 for the F pipeline
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def FEXE6 : FuncUnit; // Execution stage 6 for the F pipeline
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def FWB : FuncUnit; // Write-back unit for the F pipeline
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def LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used
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// to make sure that no lwarx/stwcx.
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// instructions are issued while another
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// lwarx/stwcx. is in the L pipe.
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def GPR_Bypass : Bypass; // The bypass for general-purpose regs.
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def FPR_Bypass : Bypass; // The bypass for floating-point regs.
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// Notes:
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// Instructions are held in the FRACC, LRACC and IRACC pipeline
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// stages until their source operands become ready. Exceptions:
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// - Store instructions will hold in the AGEN stage
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// - The integer multiply-accumulate instruction will hold in
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// the IEXE1 stage
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//
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// For most I-pipe operations, the result is available at the end of
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// the IEXE1 stage. Operations such as multiply and divide must
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// continue to execute in IEXE2 and IWB. Divide resides in IWB for
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// 33 cycles (multiply also calculates its result in IWB). For all
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// J-pipe instructions, the result is available
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// at the end of the JEXE1 stage. Loads have a 3-cycle latency
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// (data is not available until after the LWB stage).
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//
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// The L1 cache hit latency is four cycles for floating point loads
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// and three cycles for integer loads.
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//
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// The stwcx. instruction requires both the LRACC and the IRACC
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// dispatch stages. It must be issued from DISS0.
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//
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// All lwarx/stwcx. instructions hold in LRACC if another
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// uncommitted lwarx/stwcx. is in AGEN, CRD, or LWB.
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//
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// msync (a.k.a. sync) and mbar will hold in LWB until all load/store
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// resources are empty. AGEN and CRD are held empty until the msync/mbar
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// commits.
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//
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// Most floating-point instructions, computational and move,
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// have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
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// update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
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// loads take 4 cycles (for L1 hit).
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//
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// This file defines the itinerary class data for the PPC 440 processor.
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//
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//===----------------------------------------------------------------------===//
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def PPC440Itineraries : ProcessorItineraries<
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[IFTH1, IFTH2, PDCD1, PDCD2, DISS1, DISS2, FRACC,
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IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, LWB,
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FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold],
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[GPR_Bypass, FPR_Bypass], [
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InstrItinData<IntGeneral , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC, LRACC]>,
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InstrStage<1, [IEXE1, JEXE1]>,
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InstrStage<1, [IEXE2, JEXE2]>,
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InstrStage<1, [IWB, JWB]>],
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[6, 4, 4],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntCompare , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC, LRACC]>,
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InstrStage<1, [IEXE1, JEXE1]>,
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InstrStage<1, [IEXE2, JEXE2]>,
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InstrStage<1, [IWB, JWB]>],
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[6, 4, 4],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntDivW , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC]>,
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InstrStage<1, [IEXE1]>,
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InstrStage<1, [IEXE2]>,
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InstrStage<33, [IWB]>],
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[40, 4, 4],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMFFS , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC]>,
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InstrStage<1, [IEXE1]>,
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InstrStage<1, [IEXE2]>,
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InstrStage<1, [IWB]>],
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[7, 4, 4],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMTFSB0 , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC]>,
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InstrStage<1, [IEXE1]>,
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InstrStage<1, [IEXE2]>,
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InstrStage<1, [IWB]>],
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[7, 4, 4],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulHW , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC]>,
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InstrStage<1, [IEXE1]>,
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InstrStage<1, [IEXE2]>,
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InstrStage<1, [IWB]>],
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[8, 4, 4],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulHWU , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC]>,
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InstrStage<1, [IEXE1]>,
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InstrStage<1, [IEXE2]>,
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InstrStage<1, [IWB]>],
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[8, 4, 4],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntMulLI , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC]>,
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InstrStage<1, [IEXE1]>,
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InstrStage<1, [IEXE2]>,
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InstrStage<1, [IWB]>],
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[8, 4, 4],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntRotate , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC, LRACC]>,
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InstrStage<1, [IEXE1, JEXE1]>,
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InstrStage<1, [IEXE2, JEXE2]>,
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InstrStage<1, [IWB, JWB]>],
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[6, 4, 4],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntShift , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC, LRACC]>,
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InstrStage<1, [IEXE1, JEXE1]>,
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InstrStage<1, [IEXE2, JEXE2]>,
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InstrStage<1, [IWB, JWB]>],
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[6, 4, 4],
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[GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<IntTrapW , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC]>,
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InstrStage<1, [IEXE1]>,
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InstrStage<1, [IEXE2]>,
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InstrStage<1, [IWB]>],
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[6, 4],
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<BrB , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC]>,
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InstrStage<1, [IEXE1]>,
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InstrStage<1, [IEXE2]>,
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InstrStage<1, [IWB]>],
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[8, 4],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<BrCR , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC]>,
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InstrStage<1, [IEXE1]>,
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InstrStage<1, [IEXE2]>,
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InstrStage<1, [IWB]>],
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[8, 4, 4],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<BrMCR , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC]>,
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InstrStage<1, [IEXE1]>,
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InstrStage<1, [IEXE2]>,
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InstrStage<1, [IWB]>],
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[8, 4, 4],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<BrMCRX , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [IRACC]>,
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InstrStage<1, [IEXE1]>,
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InstrStage<1, [IEXE2]>,
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InstrStage<1, [IWB]>],
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[8, 4, 4],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStDCBA , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<1, [LWB]>],
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[8, 5],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStDCBF , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<1, [LWB]>],
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[8, 5],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStDCBI , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<1, [LWB]>],
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[8, 5],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStLoad , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<2, [LWB]>],
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[9, 5],
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[GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStStore , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<2, [LWB]>],
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[8, 5],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStICBI , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<1, [LWB]>],
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[8, 5],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStUX , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<1, [LWB]>],
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[8, 5, 5],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLFD , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<2, [LWB]>],
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[9, 5, 5],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLFDU , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<1, [LWB]>],
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[9, 5, 5],
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[NoBypass, GPR_Bypass, GPR_Bypass]>,
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InstrItinData<LdStLHA , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<1, [LWB]>],
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[8, 5],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStLMW , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<1, [LWB]>],
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[8, 5],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStLWARX , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1]>,
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InstrStage<1, [IRACC], 0>,
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InstrStage<4, [LWARX_Hold], 0>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<1, [LWB]>],
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[8, 5],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStSTD , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1, DISS2]>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<2, [LWB]>],
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[8, 5],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStSTDCX , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
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InstrStage<1, [DISS1]>,
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InstrStage<1, [IRACC], 0>,
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InstrStage<4, [LWARX_Hold], 0>,
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InstrStage<1, [LRACC]>,
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InstrStage<1, [AGEN]>,
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InstrStage<1, [CRD]>,
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InstrStage<1, [LWB]>],
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[8, 5],
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[NoBypass, GPR_Bypass]>,
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InstrItinData<LdStSTD , [InstrStage<1, [IFTH1, IFTH2]>,
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InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [LRACC]>,
|
|
InstrStage<1, [AGEN]>,
|
|
InstrStage<1, [CRD]>,
|
|
InstrStage<2, [LWB]>],
|
|
[8, 5],
|
|
[NoBypass, GPR_Bypass]>,
|
|
InstrItinData<LdStSTDCX , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1]>,
|
|
InstrStage<1, [IRACC], 0>,
|
|
InstrStage<4, [LWARX_Hold], 0>,
|
|
InstrStage<1, [LRACC]>,
|
|
InstrStage<1, [AGEN]>,
|
|
InstrStage<1, [CRD]>,
|
|
InstrStage<1, [LWB]>],
|
|
[8, 5],
|
|
[NoBypass, GPR_Bypass]>,
|
|
InstrItinData<LdStSTWCX , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1]>,
|
|
InstrStage<1, [IRACC], 0>,
|
|
InstrStage<4, [LWARX_Hold], 0>,
|
|
InstrStage<1, [LRACC]>,
|
|
InstrStage<1, [AGEN]>,
|
|
InstrStage<1, [CRD]>,
|
|
InstrStage<1, [LWB]>],
|
|
[8, 5],
|
|
[NoBypass, GPR_Bypass]>,
|
|
InstrItinData<LdStSync , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [LRACC]>,
|
|
InstrStage<3, [AGEN], 1>,
|
|
InstrStage<2, [CRD], 1>,
|
|
InstrStage<1, [LWB]>]>,
|
|
InstrItinData<SprISYNC , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [FRACC], 0>,
|
|
InstrStage<1, [LRACC], 0>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [FEXE1], 0>,
|
|
InstrStage<1, [AGEN], 0>,
|
|
InstrStage<1, [JEXE1], 0>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [FEXE2], 0>,
|
|
InstrStage<1, [CRD], 0>,
|
|
InstrStage<1, [JEXE2], 0>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<6, [FEXE3], 0>,
|
|
InstrStage<6, [LWB], 0>,
|
|
InstrStage<6, [JWB], 0>,
|
|
InstrStage<6, [IWB]>]>,
|
|
InstrItinData<SprMFSR , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<1, [IWB]>],
|
|
[6, 4],
|
|
[GPR_Bypass, GPR_Bypass]>,
|
|
InstrItinData<SprMTMSR , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<1, [IWB]>],
|
|
[6, 4],
|
|
[GPR_Bypass, GPR_Bypass]>,
|
|
InstrItinData<SprMTSR , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<3, [IWB]>],
|
|
[9, 4],
|
|
[NoBypass, GPR_Bypass]>,
|
|
InstrItinData<SprTLBSYNC , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<1, [IWB]>]>,
|
|
InstrItinData<SprMFCR , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<1, [IWB]>],
|
|
[8, 4],
|
|
[NoBypass, GPR_Bypass]>,
|
|
InstrItinData<SprMFMSR , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<1, [IWB]>],
|
|
[7, 4],
|
|
[GPR_Bypass, GPR_Bypass]>,
|
|
InstrItinData<SprMFSPR , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<3, [IWB]>],
|
|
[10, 4],
|
|
[NoBypass, GPR_Bypass]>,
|
|
InstrItinData<SprMFTB , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<3, [IWB]>],
|
|
[10, 4],
|
|
[NoBypass, GPR_Bypass]>,
|
|
InstrItinData<SprMTSPR , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<3, [IWB]>],
|
|
[10, 4],
|
|
[NoBypass, GPR_Bypass]>,
|
|
InstrItinData<SprMTSRIN , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<3, [IWB]>],
|
|
[10, 4],
|
|
[NoBypass, GPR_Bypass]>,
|
|
InstrItinData<SprRFI , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<1, [IWB]>],
|
|
[8, 4],
|
|
[NoBypass, GPR_Bypass]>,
|
|
InstrItinData<SprSC , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [IRACC]>,
|
|
InstrStage<1, [IEXE1]>,
|
|
InstrStage<1, [IEXE2]>,
|
|
InstrStage<1, [IWB]>],
|
|
[8, 4],
|
|
[NoBypass, GPR_Bypass]>,
|
|
InstrItinData<FPGeneral , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [FRACC]>,
|
|
InstrStage<1, [FEXE1]>,
|
|
InstrStage<1, [FEXE2]>,
|
|
InstrStage<1, [FEXE3]>,
|
|
InstrStage<1, [FEXE4]>,
|
|
InstrStage<1, [FEXE5]>,
|
|
InstrStage<1, [FEXE6]>,
|
|
InstrStage<1, [FWB]>],
|
|
[10, 4, 4],
|
|
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
|
InstrItinData<FPCompare , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [FRACC]>,
|
|
InstrStage<1, [FEXE1]>,
|
|
InstrStage<1, [FEXE2]>,
|
|
InstrStage<1, [FEXE3]>,
|
|
InstrStage<1, [FEXE4]>,
|
|
InstrStage<1, [FEXE5]>,
|
|
InstrStage<1, [FEXE6]>,
|
|
InstrStage<1, [FWB]>],
|
|
[10, 4, 4],
|
|
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
|
InstrItinData<FPDivD , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [FRACC]>,
|
|
InstrStage<1, [FEXE1]>,
|
|
InstrStage<1, [FEXE2]>,
|
|
InstrStage<1, [FEXE3]>,
|
|
InstrStage<1, [FEXE4]>,
|
|
InstrStage<1, [FEXE5]>,
|
|
InstrStage<1, [FEXE6]>,
|
|
InstrStage<25, [FWB]>],
|
|
[35, 4, 4],
|
|
[NoBypass, FPR_Bypass, FPR_Bypass]>,
|
|
InstrItinData<FPDivS , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [FRACC]>,
|
|
InstrStage<1, [FEXE1]>,
|
|
InstrStage<1, [FEXE2]>,
|
|
InstrStage<1, [FEXE3]>,
|
|
InstrStage<1, [FEXE4]>,
|
|
InstrStage<1, [FEXE5]>,
|
|
InstrStage<1, [FEXE6]>,
|
|
InstrStage<13, [FWB]>],
|
|
[23, 4, 4],
|
|
[NoBypass, FPR_Bypass, FPR_Bypass]>,
|
|
InstrItinData<FPFused , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [FRACC]>,
|
|
InstrStage<1, [FEXE1]>,
|
|
InstrStage<1, [FEXE2]>,
|
|
InstrStage<1, [FEXE3]>,
|
|
InstrStage<1, [FEXE4]>,
|
|
InstrStage<1, [FEXE5]>,
|
|
InstrStage<1, [FEXE6]>,
|
|
InstrStage<1, [FWB]>],
|
|
[10, 4, 4, 4],
|
|
[FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
|
|
InstrItinData<FPRes , [InstrStage<1, [IFTH1, IFTH2]>,
|
|
InstrStage<1, [PDCD1, PDCD2]>,
|
|
InstrStage<1, [DISS1, DISS2]>,
|
|
InstrStage<1, [FRACC]>,
|
|
InstrStage<1, [FEXE1]>,
|
|
InstrStage<1, [FEXE2]>,
|
|
InstrStage<1, [FEXE3]>,
|
|
InstrStage<1, [FEXE4]>,
|
|
InstrStage<1, [FEXE5]>,
|
|
InstrStage<1, [FEXE6]>,
|
|
InstrStage<1, [FWB]>],
|
|
[10, 4],
|
|
[FPR_Bypass, FPR_Bypass]>
|
|
]>;
|