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https://github.com/c64scene-ar/llvm-6502.git
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e5609f3732
Previously LEA64_32r went through virtually the entire backend thinking it was using 32-bit registers until its blissful illusions were cruelly snatched away by MCInstLower and 64-bit equivalents were substituted at the last minute. This patch makes it behave normally, and take 64-bit registers as sources all the way through. Previous uses (for 32-bit arithmetic) are accommodated via SUBREG_TO_REG instructions which make the types and classes agree properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183693 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
1.7 KiB
LLVM
59 lines
1.7 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin10.0.0"
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define i32 @f(i32 %x) nounwind ssp {
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entry:
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%shl.i = shl i32 %x, 12
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%neg.i = xor i32 %shl.i, -1
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%add.i = add nsw i32 %neg.i, %x
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%shr.i = ashr i32 %add.i, 22
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%xor.i = xor i32 %shr.i, %add.i
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%shl5.i = shl i32 %xor.i, 13
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%neg6.i = xor i32 %shl5.i, -1
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%add8.i = add nsw i32 %xor.i, %neg6.i
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%shr10.i = ashr i32 %add8.i, 8
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%xor12.i = xor i32 %shr10.i, %add8.i
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%add16.i = mul i32 %xor12.i, 9
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%shr18.i = ashr i32 %add16.i, 15
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%xor20.i = xor i32 %shr18.i, %add16.i
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%shl22.i = shl i32 %xor20.i, 27
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%neg23.i = xor i32 %shl22.i, -1
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%add25.i = add nsw i32 %xor20.i, %neg23.i
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%shr27.i = ashr i32 %add25.i, 31
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%rem = srem i32 %x, 7
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%cmp = icmp eq i32 %rem, 3
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br i1 %cmp, label %land.lhs.true, label %do.body.preheader
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land.lhs.true:
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%call3 = tail call i32 @g(i32 %x) nounwind
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%cmp4 = icmp eq i32 %call3, 10
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br i1 %cmp4, label %do.body.preheader, label %if.then
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; %add16.i should be sinked all the way down to do.body.preheader, but not into the loop.
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; CHECK: do.body.preheader
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; CHECK-NOT: do.body
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; CHECK: leal ([[SRC:%r[a-z0-9]+]],[[SRC]],8)
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do.body.preheader:
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%xor29.i = xor i32 %shr27.i, %add25.i
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br label %do.body
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if.then:
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%add = add nsw i32 %x, 11
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ret i32 %add
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do.body:
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%x.addr.1 = phi i32 [ %add9, %do.body ], [ %x, %do.body.preheader ]
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%xor = xor i32 %xor29.i, %x.addr.1
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%add9 = add nsw i32 %xor, %x.addr.1
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%and = and i32 %add9, 13
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%tobool = icmp eq i32 %and, 0
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br i1 %tobool, label %if.end, label %do.body
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if.end:
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ret i32 %add9
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}
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declare i32 @g(i32)
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