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define below all header includes in the lib/CodeGen/... tree. While the current modules implementation doesn't check for this kind of ODR violation yet, it is likely to grow support for it in the future. It also removes one layer of macro pollution across all the included headers. Other sub-trees will follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206837 91177308-0d34-0410-b5e6-96231b3b80d8
180 lines
6.2 KiB
C++
180 lines
6.2 KiB
C++
//===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RegisterClassInfo class which provides dynamic
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// information about target register classes. Callee-saved vs. caller-saved and
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// reserved registers depend on calling conventions and other dynamic
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// information, so some things cannot be determined statically.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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static cl::opt<unsigned>
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StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
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cl::desc("Limit all regclasses to N registers"));
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RegisterClassInfo::RegisterClassInfo()
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: Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {}
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void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
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bool Update = false;
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MF = &mf;
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// Allocate new array the first time we see a new target.
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if (MF->getTarget().getRegisterInfo() != TRI) {
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TRI = MF->getTarget().getRegisterInfo();
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RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
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unsigned NumPSets = TRI->getNumRegPressureSets();
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PSetLimits.reset(new unsigned[NumPSets]);
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std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
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Update = true;
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}
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// Does this MF have different CSRs?
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const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
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if (Update || CSR != CalleeSaved) {
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// Build a CSRNum map. Every CSR alias gets an entry pointing to the last
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// overlapping CSR.
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CSRNum.clear();
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CSRNum.resize(TRI->getNumRegs(), 0);
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for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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CSRNum[*AI] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
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Update = true;
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}
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CalleeSaved = CSR;
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// Different reserved registers?
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const BitVector &RR = MF->getRegInfo().getReservedRegs();
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if (Reserved.size() != RR.size() || RR != Reserved) {
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Update = true;
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Reserved = RR;
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}
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// Invalidate cached information from previous function.
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if (Update)
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++Tag;
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}
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/// compute - Compute the preferred allocation order for RC with reserved
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/// registers filtered out. Volatile registers come first followed by CSR
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/// aliases ordered according to the CSR order specified by the target.
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void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
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RCInfo &RCI = RegClass[RC->getID()];
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// Raw register count, including all reserved regs.
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unsigned NumRegs = RC->getNumRegs();
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if (!RCI.Order)
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RCI.Order.reset(new MCPhysReg[NumRegs]);
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unsigned N = 0;
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SmallVector<MCPhysReg, 16> CSRAlias;
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unsigned MinCost = 0xff;
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unsigned LastCost = ~0u;
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unsigned LastCostChange = 0;
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// FIXME: Once targets reserve registers instead of removing them from the
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// allocation order, we can simply use begin/end here.
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ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
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for (unsigned i = 0; i != RawOrder.size(); ++i) {
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unsigned PhysReg = RawOrder[i];
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// Remove reserved registers from the allocation order.
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if (Reserved.test(PhysReg))
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continue;
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unsigned Cost = TRI->getCostPerUse(PhysReg);
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MinCost = std::min(MinCost, Cost);
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if (CSRNum[PhysReg])
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// PhysReg aliases a CSR, save it for later.
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CSRAlias.push_back(PhysReg);
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else {
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if (Cost != LastCost)
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LastCostChange = N;
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RCI.Order[N++] = PhysReg;
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LastCost = Cost;
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}
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}
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RCI.NumRegs = N + CSRAlias.size();
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assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
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// CSR aliases go after the volatile registers, preserve the target's order.
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for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
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unsigned PhysReg = CSRAlias[i];
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unsigned Cost = TRI->getCostPerUse(PhysReg);
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if (Cost != LastCost)
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LastCostChange = N;
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RCI.Order[N++] = PhysReg;
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LastCost = Cost;
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}
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// Register allocator stress test. Clip register class to N registers.
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if (StressRA && RCI.NumRegs > StressRA)
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RCI.NumRegs = StressRA;
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// Check if RC is a proper sub-class.
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if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
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if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
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RCI.ProperSubClass = true;
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RCI.MinCost = uint8_t(MinCost);
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RCI.LastCostChange = LastCostChange;
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DEBUG({
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dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
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for (unsigned I = 0; I != RCI.NumRegs; ++I)
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dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
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dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
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});
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// RCI is now up-to-date.
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RCI.Tag = Tag;
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}
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/// This is not accurate because two overlapping register sets may have some
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/// nonoverlapping reserved registers. However, computing the allocation order
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/// for all register classes would be too expensive.
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unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
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const TargetRegisterClass *RC = nullptr;
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unsigned NumRCUnits = 0;
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for (TargetRegisterInfo::regclass_iterator
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RI = TRI->regclass_begin(), RE = TRI->regclass_end(); RI != RE; ++RI) {
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const int *PSetID = TRI->getRegClassPressureSets(*RI);
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for (; *PSetID != -1; ++PSetID) {
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if ((unsigned)*PSetID == Idx)
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break;
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}
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if (*PSetID == -1)
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continue;
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// Found a register class that counts against this pressure set.
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// For efficiency, only compute the set order for the largest set.
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unsigned NUnits = TRI->getRegClassWeight(*RI).WeightLimit;
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if (!RC || NUnits > NumRCUnits) {
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RC = *RI;
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NumRCUnits = NUnits;
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}
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}
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compute(RC);
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unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
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return TRI->getRegPressureSetLimit(Idx)
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- TRI->getRegClassWeight(RC).RegWeight * NReserved;
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}
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