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8db9fbf7cd
SeparateConstOffsetFromGEP can gives more optimizaiton opportunities related to GEPs, which benefits EarlyCSE and LICM. By enabling these passes we can have better address calculations and generate a better addressing mode. Some SPEC 2006 benchmarks (astar, gobmk, namd) have obvious improvements on Cortex-A57. Reviewed in http://reviews.llvm.org/D5864. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222331 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
1.4 KiB
LLVM
60 lines
1.4 KiB
LLVM
; RUN: llc -O3 < %s -aarch64-atomic-cfg-tidy=0 -aarch64-gep-opt=false | FileCheck %s
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target triple = "arm64-apple-ios"
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; rdar://12462006
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; CSE between "icmp reg reg" and "sub reg reg".
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; Both can be in the same basic block or in different basic blocks.
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define i8* @t1(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: subs
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; CHECK-NOT: cmp
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; CHECK-NOT: sub
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; CHECK: b.ge
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; CHECK: sub
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; CHECK: sub
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; CHECK-NOT: sub
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; CHECK: ret
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%0 = load i32* %offset, align 4
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%cmp = icmp slt i32 %0, %size
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%s = sub nsw i32 %0, %size
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br i1 %cmp, label %return, label %if.end
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if.end:
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%sub = sub nsw i32 %0, %size
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%s2 = sub nsw i32 %s, %size
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%s3 = sub nsw i32 %sub, %s2
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store i32 %s3, i32* %offset, align 4
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%add.ptr = getelementptr inbounds i8* %base, i32 %sub
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br label %return
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return:
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%retval.0 = phi i8* [ %add.ptr, %if.end ], [ null, %entry ]
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ret i8* %retval.0
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}
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; CSE between "icmp reg imm" and "sub reg imm".
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define i8* @t2(i8* %base, i32* nocapture %offset) nounwind {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: subs
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; CHECK-NOT: cmp
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; CHECK-NOT: sub
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; CHECK: b.lt
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; CHECK-NOT: sub
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; CHECK: ret
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%0 = load i32* %offset, align 4
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%cmp = icmp slt i32 %0, 1
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br i1 %cmp, label %return, label %if.end
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if.end:
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%sub = sub nsw i32 %0, 1
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store i32 %sub, i32* %offset, align 4
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%add.ptr = getelementptr inbounds i8* %base, i32 %sub
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br label %return
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return:
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%retval.0 = phi i8* [ %add.ptr, %if.end ], [ null, %entry ]
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ret i8* %retval.0
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}
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