Evan Cheng ccb6976a69 Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8		2009-01-02 05:35:45 +00:00
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Alpha
ARM
CBackend
CellSPU	Fix PR3274: when promoting the condition of a BRCOND node,	2009-01-01 15:52:00 +00:00
CPP
Generic
IA64
Mips
PowerPC	rename a file to follow naming conventions.	2009-01-02 01:52:35 +00:00
SPARC
X86	Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.	2009-01-02 05:35:45 +00:00
XCore