mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
65 lines
2.2 KiB
LLVM
65 lines
2.2 KiB
LLVM
; RUN: opt < %s -tailcallelim -S | grep call | count 3
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; PR4323
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; Several cases where tail call elimination should not move the load above the
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; call, and thus can't eliminate the tail recursion.
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@extern_weak_global = extern_weak global i32 ; <i32*> [#uses=1]
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; This load can't be safely moved above the call because the load is from an
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; extern_weak global and may trap, but the call may unwind before that happens.
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define fastcc i32 @no_tailrecelim_1(i32* %a_arg, i32 %a_len_arg, i32 %start_arg) readonly {
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entry:
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%tmp2 = icmp sge i32 %start_arg, %a_len_arg ; <i1> [#uses=1]
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br i1 %tmp2, label %if, label %else
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if: ; preds = %entry
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ret i32 37
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else: ; preds = %entry
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%tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
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%tmp8 = call fastcc i32 @no_tailrecelim_1(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
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%tmp9 = load i32, i32* @extern_weak_global ; <i32> [#uses=1]
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%tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
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ret i32 %tmp10
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}
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; This load can't be safely moved above the call because function may write to the pointer.
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define fastcc i32 @no_tailrecelim_2(i32* %a_arg, i32 %a_len_arg, i32 %start_arg) nounwind {
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entry:
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%tmp2 = icmp sge i32 %start_arg, %a_len_arg ; <i1> [#uses=1]
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br i1 %tmp2, label %if, label %else
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if: ; preds = %entry
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store i32 1, i32* %a_arg
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ret i32 0
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else: ; preds = %entry
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%tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
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%tmp8 = call fastcc i32 @no_tailrecelim_2(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
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%tmp9 = load i32, i32* %a_arg ; <i32> [#uses=1]
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%tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
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ret i32 %tmp10
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}
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; This load can't be safely moved above the call because that would change the
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; order in which the load volatiles are performed.
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define fastcc i32 @no_tailrecelim_3(i32* %a_arg, i32 %a_len_arg, i32 %start_arg) nounwind {
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entry:
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%tmp2 = icmp sge i32 %start_arg, %a_len_arg ; <i1> [#uses=1]
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br i1 %tmp2, label %if, label %else
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if: ; preds = %entry
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ret i32 0
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else: ; preds = %entry
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%tmp7 = add i32 %start_arg, 1 ; <i32> [#uses=1]
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%tmp8 = call fastcc i32 @no_tailrecelim_3(i32* %a_arg, i32 %a_len_arg, i32 %tmp7) ; <i32> [#uses=1]
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%tmp9 = load volatile i32, i32* %a_arg ; <i32> [#uses=1]
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%tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=1]
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ret i32 %tmp10
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}
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