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https://github.com/c64scene-ar/llvm-6502.git
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d8b7dd5252
permutations. Also tidy up some patterns and make them close to their instruction definition! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138392 91177308-0d34-0410-b5e6-96231b3b80d8
104 lines
4.0 KiB
LLVM
104 lines
4.0 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; CHECK: vpunpcklbw %xmm
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; CHECK-NEXT: vpunpckhbw %xmm
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; CHECK-NEXT: vinsertf128 $1
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; CHECK-NEXT: vpermilps $85
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define <32 x i8> @funcA(<32 x i8> %a) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
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ret <32 x i8> %shuffle
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}
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; CHECK: vpunpckhwd %xmm
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; CHECK-NEXT: vinsertf128 $1
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; CHECK-NEXT: vpermilps $85
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define <16 x i16> @funcB(<16 x i16> %a) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
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ret <16 x i16> %shuffle
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}
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; CHECK: vmovd
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; CHECK-NEXT: vmovlhps %xmm
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; CHECK-NEXT: vinsertf128 $1
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define <4 x i64> @funcC(i64 %q) nounwind uwtable readnone ssp {
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entry:
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%vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
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%vecinit2.i = insertelement <4 x i64> %vecinit.i, i64 %q, i32 1
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%vecinit4.i = insertelement <4 x i64> %vecinit2.i, i64 %q, i32 2
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%vecinit6.i = insertelement <4 x i64> %vecinit4.i, i64 %q, i32 3
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ret <4 x i64> %vecinit6.i
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}
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; CHECK: vshufpd $0
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; CHECK-NEXT: vinsertf128 $1
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define <4 x double> @funcD(double %q) nounwind uwtable readnone ssp {
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entry:
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%vecinit.i = insertelement <4 x double> undef, double %q, i32 0
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%vecinit2.i = insertelement <4 x double> %vecinit.i, double %q, i32 1
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%vecinit4.i = insertelement <4 x double> %vecinit2.i, double %q, i32 2
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%vecinit6.i = insertelement <4 x double> %vecinit4.i, double %q, i32 3
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ret <4 x double> %vecinit6.i
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}
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; Test this simple opt:
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; shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
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; To:
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; shuffle (vload ptr)), undef, <1, 1, 1, 1>
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; CHECK: vmovaps
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; CHECK-NEXT: vinsertf128 $1
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; CHECK-NEXT: vpermilps $-1
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define <8 x float> @funcE() nounwind {
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allocas:
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%udx495 = alloca [18 x [18 x float]], align 32
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br label %for_test505.preheader
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for_test505.preheader: ; preds = %for_test505.preheader, %allocas
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br i1 undef, label %for_exit499, label %for_test505.preheader
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for_exit499: ; preds = %for_test505.preheader
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br i1 undef, label %__load_and_broadcast_32.exit1249, label %load.i1247
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load.i1247: ; preds = %for_exit499
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%ptr1227 = getelementptr [18 x [18 x float]]* %udx495, i64 0, i64 1, i64 1
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%ptr.i1237 = bitcast float* %ptr1227 to i32*
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%val.i1238 = load i32* %ptr.i1237, align 4
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%ret6.i1245 = insertelement <8 x i32> undef, i32 %val.i1238, i32 6
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%ret7.i1246 = insertelement <8 x i32> %ret6.i1245, i32 %val.i1238, i32 7
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%phitmp = bitcast <8 x i32> %ret7.i1246 to <8 x float>
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br label %__load_and_broadcast_32.exit1249
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__load_and_broadcast_32.exit1249: ; preds = %load.i1247, %for_exit499
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%load_broadcast12281250 = phi <8 x float> [ %phitmp, %load.i1247 ], [ undef, %for_exit499 ]
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ret <8 x float> %load_broadcast12281250
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}
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; CHECK: vinsertf128 $1
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; CHECK-NEXT: vpermilps $0
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define <8 x float> @funcF(i32 %val) nounwind {
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%ret6 = insertelement <8 x i32> undef, i32 %val, i32 6
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%ret7 = insertelement <8 x i32> %ret6, i32 %val, i32 7
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%tmp = bitcast <8 x i32> %ret7 to <8 x float>
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ret <8 x float> %tmp
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}
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; CHECK: vinsertf128 $1
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; CHECK-NEXT: vpermilps $0
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define <8 x float> @funcG(<8 x float> %a) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x float> %shuffle
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}
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; CHECK: vextractf128 $1
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; CHECK-NEXT: vinsertf128 $1
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; CHECK-NEXT: vpermilps $85
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define <8 x float> @funcH(<8 x float> %a) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
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ret <8 x float> %shuffle
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}
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