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77ed1353bf
processor supports it just fine. Fixes PR9675 and rdar://9740801 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134664 91177308-0d34-0410-b5e6-96231b3b80d8
16 lines
512 B
LLVM
16 lines
512 B
LLVM
; RUN: llc < %s -march=x86-64 -mattr=-sse -O0
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; PR9675
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define i32 @t() {
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entry:
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%i = alloca i32, align 4
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store i32 1, i32* %i, align 4
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call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
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%0 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %i, i32 1)
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call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
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ret i32 0
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}
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declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* nocapture, i32) nounwind
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declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
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