llvm-6502/test/CodeGen
2014-09-11 10:29:42 +00:00
..
AArch64 Build correct vector filled with undef nodes 2014-09-11 05:10:28 +00:00
ARM [ARM] Add Thumb2 code size optimization regression test for LSL (immediate). 2014-09-11 10:29:42 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430 Drop the W postfix on the 16-bit registers. 2014-09-10 06:58:14 +00:00
NVPTX
PowerPC
R600 R600/SI: Fix losing chain when fixing reg class of loads. 2014-09-10 23:26:19 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86 [x86] Fixup r217565 which baked in an assumption about the function 2014-09-11 10:21:25 +00:00
XCore