mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f67c7d7e8c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186311 91177308-0d34-0410-b5e6-96231b3b80d8
511 lines
18 KiB
C++
511 lines
18 KiB
C++
//=- AArch64/AArch64MCCodeEmitter.cpp - Convert AArch64 code to machine code =//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AArch64MCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mccodeemitter"
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#include "MCTargetDesc/AArch64FixupKinds.h"
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#include "MCTargetDesc/AArch64MCExpr.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class AArch64MCCodeEmitter : public MCCodeEmitter {
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AArch64MCCodeEmitter(const AArch64MCCodeEmitter &) LLVM_DELETED_FUNCTION;
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void operator=(const AArch64MCCodeEmitter &) LLVM_DELETED_FUNCTION;
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MCContext &Ctx;
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public:
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AArch64MCCodeEmitter(MCContext &ctx) : Ctx(ctx) {}
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~AArch64MCCodeEmitter() {}
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unsigned getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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template<int MemSize>
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unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return getOffsetUImm12OpValue(MI, OpIdx, Fixups, MemSize);
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}
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unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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int MemSize) const;
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unsigned getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// Labels are handled mostly the same way: a symbol is needed, and
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// just gets some fixup attached.
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template<AArch64::Fixups fixupDesired>
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unsigned getLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getLoadLitLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getAddressWithFixup(const MCOperand &MO,
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unsigned FixupKind,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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void EmitByte(unsigned char C, raw_ostream &OS) const {
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OS << (char)C;
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}
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void EmitInstruction(uint32_t Val, raw_ostream &OS) const {
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// Output the constant in little endian byte order.
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for (unsigned i = 0; i != 4; ++i) {
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EmitByte(Val & 0xff, OS);
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Val >>= 8;
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}
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}
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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template<int hasRs, int hasRt2> unsigned
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fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue) const;
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unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue) const;
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unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue) const;
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};
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} // end anonymous namespace
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unsigned AArch64MCCodeEmitter::getAddressWithFixup(const MCOperand &MO,
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unsigned FixupKind,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (!MO.isExpr()) {
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// This can occur for manually decoded or constructed MCInsts, but neither
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// the assembly-parser nor instruction selection will currently produce an
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// MCInst that's not a symbol reference.
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assert(MO.isImm() && "Unexpected address requested");
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return MO.getImm();
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}
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const MCExpr *Expr = MO.getExpr();
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MCFixupKind Kind = MCFixupKind(FixupKind);
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Fixups.push_back(MCFixup::Create(0, Expr, Kind));
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return 0;
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}
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unsigned AArch64MCCodeEmitter::
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getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups,
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int MemSize) const {
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const MCOperand &ImmOp = MI.getOperand(OpIdx);
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if (ImmOp.isImm())
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return ImmOp.getImm();
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assert(ImmOp.isExpr() && "Unexpected operand type");
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const AArch64MCExpr *Expr = cast<AArch64MCExpr>(ImmOp.getExpr());
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unsigned FixupKind;
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switch (Expr->getKind()) {
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default: llvm_unreachable("Unexpected operand modifier");
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case AArch64MCExpr::VK_AARCH64_LO12: {
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static const unsigned FixupsBySize[] = { AArch64::fixup_a64_ldst8_lo12,
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AArch64::fixup_a64_ldst16_lo12,
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AArch64::fixup_a64_ldst32_lo12,
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AArch64::fixup_a64_ldst64_lo12,
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AArch64::fixup_a64_ldst128_lo12 };
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assert(MemSize <= 16 && "Invalid fixup for operation");
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FixupKind = FixupsBySize[Log2_32(MemSize)];
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break;
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}
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case AArch64MCExpr::VK_AARCH64_GOT_LO12:
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assert(MemSize == 8 && "Invalid fixup for operation");
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FixupKind = AArch64::fixup_a64_ld64_got_lo12_nc;
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break;
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case AArch64MCExpr::VK_AARCH64_DTPREL_LO12: {
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static const unsigned FixupsBySize[] = {
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AArch64::fixup_a64_ldst8_dtprel_lo12,
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AArch64::fixup_a64_ldst16_dtprel_lo12,
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AArch64::fixup_a64_ldst32_dtprel_lo12,
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AArch64::fixup_a64_ldst64_dtprel_lo12
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};
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assert(MemSize <= 8 && "Invalid fixup for operation");
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FixupKind = FixupsBySize[Log2_32(MemSize)];
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break;
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}
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case AArch64MCExpr::VK_AARCH64_DTPREL_LO12_NC: {
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static const unsigned FixupsBySize[] = {
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AArch64::fixup_a64_ldst8_dtprel_lo12_nc,
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AArch64::fixup_a64_ldst16_dtprel_lo12_nc,
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AArch64::fixup_a64_ldst32_dtprel_lo12_nc,
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AArch64::fixup_a64_ldst64_dtprel_lo12_nc
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};
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assert(MemSize <= 8 && "Invalid fixup for operation");
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FixupKind = FixupsBySize[Log2_32(MemSize)];
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break;
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}
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case AArch64MCExpr::VK_AARCH64_GOTTPREL_LO12:
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assert(MemSize == 8 && "Invalid fixup for operation");
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FixupKind = AArch64::fixup_a64_ld64_gottprel_lo12_nc;
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break;
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case AArch64MCExpr::VK_AARCH64_TPREL_LO12:{
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static const unsigned FixupsBySize[] = {
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AArch64::fixup_a64_ldst8_tprel_lo12,
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AArch64::fixup_a64_ldst16_tprel_lo12,
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AArch64::fixup_a64_ldst32_tprel_lo12,
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AArch64::fixup_a64_ldst64_tprel_lo12
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};
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assert(MemSize <= 8 && "Invalid fixup for operation");
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FixupKind = FixupsBySize[Log2_32(MemSize)];
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break;
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}
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case AArch64MCExpr::VK_AARCH64_TPREL_LO12_NC: {
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static const unsigned FixupsBySize[] = {
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AArch64::fixup_a64_ldst8_tprel_lo12_nc,
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AArch64::fixup_a64_ldst16_tprel_lo12_nc,
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AArch64::fixup_a64_ldst32_tprel_lo12_nc,
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AArch64::fixup_a64_ldst64_tprel_lo12_nc
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};
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assert(MemSize <= 8 && "Invalid fixup for operation");
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FixupKind = FixupsBySize[Log2_32(MemSize)];
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break;
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}
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case AArch64MCExpr::VK_AARCH64_TLSDESC_LO12:
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assert(MemSize == 8 && "Invalid fixup for operation");
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FixupKind = AArch64::fixup_a64_tlsdesc_ld64_lo12_nc;
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break;
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}
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return getAddressWithFixup(ImmOp, FixupKind, Fixups);
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}
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unsigned
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AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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assert(MO.isExpr());
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unsigned FixupKind = 0;
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switch(cast<AArch64MCExpr>(MO.getExpr())->getKind()) {
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default: llvm_unreachable("Invalid expression modifier");
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case AArch64MCExpr::VK_AARCH64_LO12:
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FixupKind = AArch64::fixup_a64_add_lo12; break;
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case AArch64MCExpr::VK_AARCH64_DTPREL_HI12:
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FixupKind = AArch64::fixup_a64_add_dtprel_hi12; break;
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case AArch64MCExpr::VK_AARCH64_DTPREL_LO12:
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FixupKind = AArch64::fixup_a64_add_dtprel_lo12; break;
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case AArch64MCExpr::VK_AARCH64_DTPREL_LO12_NC:
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FixupKind = AArch64::fixup_a64_add_dtprel_lo12_nc; break;
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case AArch64MCExpr::VK_AARCH64_TPREL_HI12:
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FixupKind = AArch64::fixup_a64_add_tprel_hi12; break;
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case AArch64MCExpr::VK_AARCH64_TPREL_LO12:
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FixupKind = AArch64::fixup_a64_add_tprel_lo12; break;
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case AArch64MCExpr::VK_AARCH64_TPREL_LO12_NC:
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FixupKind = AArch64::fixup_a64_add_tprel_lo12_nc; break;
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case AArch64MCExpr::VK_AARCH64_TLSDESC_LO12:
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FixupKind = AArch64::fixup_a64_tlsdesc_add_lo12_nc; break;
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}
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return getAddressWithFixup(MO, FixupKind, Fixups);
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}
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unsigned
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AArch64MCCodeEmitter::getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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assert(MO.isExpr());
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unsigned Modifier = AArch64MCExpr::VK_AARCH64_None;
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if (const AArch64MCExpr *Expr = dyn_cast<AArch64MCExpr>(MO.getExpr()))
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Modifier = Expr->getKind();
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unsigned FixupKind = 0;
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switch(Modifier) {
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case AArch64MCExpr::VK_AARCH64_None:
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FixupKind = AArch64::fixup_a64_adr_prel_page;
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break;
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case AArch64MCExpr::VK_AARCH64_GOT:
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FixupKind = AArch64::fixup_a64_adr_prel_got_page;
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break;
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case AArch64MCExpr::VK_AARCH64_GOTTPREL:
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FixupKind = AArch64::fixup_a64_adr_gottprel_page;
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break;
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case AArch64MCExpr::VK_AARCH64_TLSDESC:
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FixupKind = AArch64::fixup_a64_tlsdesc_adr_page;
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break;
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default:
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llvm_unreachable("Unknown symbol reference kind for ADRP instruction");
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}
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return getAddressWithFixup(MO, FixupKind, Fixups);
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}
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unsigned
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AArch64MCCodeEmitter::getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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assert(MO.isImm() && "Only immediate expected for shift");
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return ((32 - MO.getImm()) & 0x1f) | (31 - MO.getImm()) << 6;
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}
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unsigned
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AArch64MCCodeEmitter::getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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assert(MO.isImm() && "Only immediate expected for shift");
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return ((64 - MO.getImm()) & 0x3f) | (63 - MO.getImm()) << 6;
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}
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template<AArch64::Fixups fixupDesired> unsigned
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AArch64MCCodeEmitter::getLabelOpValue(const MCInst &MI,
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unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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if (MO.isExpr())
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return getAddressWithFixup(MO, fixupDesired, Fixups);
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assert(MO.isImm());
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return MO.getImm();
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}
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unsigned
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AArch64MCCodeEmitter::getLoadLitLabelOpValue(const MCInst &MI,
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unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &MO = MI.getOperand(OpIdx);
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if (MO.isImm())
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return MO.getImm();
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assert(MO.isExpr());
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unsigned FixupKind;
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if (isa<AArch64MCExpr>(MO.getExpr())) {
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assert(dyn_cast<AArch64MCExpr>(MO.getExpr())->getKind()
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== AArch64MCExpr::VK_AARCH64_GOTTPREL
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&& "Invalid symbol modifier for literal load");
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FixupKind = AArch64::fixup_a64_ld_gottprel_prel19;
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} else {
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FixupKind = AArch64::fixup_a64_ld_prel;
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}
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return getAddressWithFixup(MO, FixupKind, Fixups);
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}
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unsigned
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AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI,
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const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (MO.isReg()) {
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return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
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} else if (MO.isImm()) {
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return static_cast<unsigned>(MO.getImm());
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}
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llvm_unreachable("Unable to encode MCOperand!");
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return 0;
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}
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unsigned
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AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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const MCOperand &UImm16MO = MI.getOperand(OpIdx);
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const MCOperand &ShiftMO = MI.getOperand(OpIdx + 1);
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unsigned Result = static_cast<unsigned>(ShiftMO.getImm()) << 16;
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if (UImm16MO.isImm()) {
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Result |= UImm16MO.getImm();
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return Result;
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}
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const AArch64MCExpr *A64E = cast<AArch64MCExpr>(UImm16MO.getExpr());
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AArch64::Fixups requestedFixup;
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switch (A64E->getKind()) {
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default: llvm_unreachable("unexpected expression modifier");
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case AArch64MCExpr::VK_AARCH64_ABS_G0:
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requestedFixup = AArch64::fixup_a64_movw_uabs_g0; break;
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case AArch64MCExpr::VK_AARCH64_ABS_G0_NC:
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requestedFixup = AArch64::fixup_a64_movw_uabs_g0_nc; break;
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case AArch64MCExpr::VK_AARCH64_ABS_G1:
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requestedFixup = AArch64::fixup_a64_movw_uabs_g1; break;
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case AArch64MCExpr::VK_AARCH64_ABS_G1_NC:
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requestedFixup = AArch64::fixup_a64_movw_uabs_g1_nc; break;
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case AArch64MCExpr::VK_AARCH64_ABS_G2:
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requestedFixup = AArch64::fixup_a64_movw_uabs_g2; break;
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case AArch64MCExpr::VK_AARCH64_ABS_G2_NC:
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requestedFixup = AArch64::fixup_a64_movw_uabs_g2_nc; break;
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case AArch64MCExpr::VK_AARCH64_ABS_G3:
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requestedFixup = AArch64::fixup_a64_movw_uabs_g3; break;
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case AArch64MCExpr::VK_AARCH64_SABS_G0:
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requestedFixup = AArch64::fixup_a64_movw_sabs_g0; break;
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case AArch64MCExpr::VK_AARCH64_SABS_G1:
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requestedFixup = AArch64::fixup_a64_movw_sabs_g1; break;
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case AArch64MCExpr::VK_AARCH64_SABS_G2:
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requestedFixup = AArch64::fixup_a64_movw_sabs_g2; break;
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case AArch64MCExpr::VK_AARCH64_DTPREL_G2:
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requestedFixup = AArch64::fixup_a64_movw_dtprel_g2; break;
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case AArch64MCExpr::VK_AARCH64_DTPREL_G1:
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requestedFixup = AArch64::fixup_a64_movw_dtprel_g1; break;
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case AArch64MCExpr::VK_AARCH64_DTPREL_G1_NC:
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requestedFixup = AArch64::fixup_a64_movw_dtprel_g1_nc; break;
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case AArch64MCExpr::VK_AARCH64_DTPREL_G0:
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requestedFixup = AArch64::fixup_a64_movw_dtprel_g0; break;
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case AArch64MCExpr::VK_AARCH64_DTPREL_G0_NC:
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requestedFixup = AArch64::fixup_a64_movw_dtprel_g0_nc; break;
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case AArch64MCExpr::VK_AARCH64_GOTTPREL_G1:
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requestedFixup = AArch64::fixup_a64_movw_gottprel_g1; break;
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case AArch64MCExpr::VK_AARCH64_GOTTPREL_G0_NC:
|
|
requestedFixup = AArch64::fixup_a64_movw_gottprel_g0_nc; break;
|
|
case AArch64MCExpr::VK_AARCH64_TPREL_G2:
|
|
requestedFixup = AArch64::fixup_a64_movw_tprel_g2; break;
|
|
case AArch64MCExpr::VK_AARCH64_TPREL_G1:
|
|
requestedFixup = AArch64::fixup_a64_movw_tprel_g1; break;
|
|
case AArch64MCExpr::VK_AARCH64_TPREL_G1_NC:
|
|
requestedFixup = AArch64::fixup_a64_movw_tprel_g1_nc; break;
|
|
case AArch64MCExpr::VK_AARCH64_TPREL_G0:
|
|
requestedFixup = AArch64::fixup_a64_movw_tprel_g0; break;
|
|
case AArch64MCExpr::VK_AARCH64_TPREL_G0_NC:
|
|
requestedFixup = AArch64::fixup_a64_movw_tprel_g0_nc; break;
|
|
}
|
|
|
|
return Result | getAddressWithFixup(UImm16MO, requestedFixup, Fixups);
|
|
}
|
|
|
|
template<int hasRs, int hasRt2> unsigned
|
|
AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
|
|
unsigned EncodedValue) const {
|
|
if (!hasRs) EncodedValue |= 0x001F0000;
|
|
if (!hasRt2) EncodedValue |= 0x00007C00;
|
|
|
|
return EncodedValue;
|
|
}
|
|
|
|
unsigned
|
|
AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue) const {
|
|
// If one of the signed fixup kinds is applied to a MOVZ instruction, the
|
|
// eventual result could be either a MOVZ or a MOVN. It's the MCCodeEmitter's
|
|
// job to ensure that any bits possibly affected by this are 0. This means we
|
|
// must zero out bit 30 (essentially emitting a MOVN).
|
|
MCOperand UImm16MO = MI.getOperand(1);
|
|
|
|
// Nothing to do if there's no fixup.
|
|
if (UImm16MO.isImm())
|
|
return EncodedValue;
|
|
|
|
const AArch64MCExpr *A64E = cast<AArch64MCExpr>(UImm16MO.getExpr());
|
|
switch (A64E->getKind()) {
|
|
case AArch64MCExpr::VK_AARCH64_SABS_G0:
|
|
case AArch64MCExpr::VK_AARCH64_SABS_G1:
|
|
case AArch64MCExpr::VK_AARCH64_SABS_G2:
|
|
case AArch64MCExpr::VK_AARCH64_DTPREL_G2:
|
|
case AArch64MCExpr::VK_AARCH64_DTPREL_G1:
|
|
case AArch64MCExpr::VK_AARCH64_DTPREL_G0:
|
|
case AArch64MCExpr::VK_AARCH64_GOTTPREL_G1:
|
|
case AArch64MCExpr::VK_AARCH64_TPREL_G2:
|
|
case AArch64MCExpr::VK_AARCH64_TPREL_G1:
|
|
case AArch64MCExpr::VK_AARCH64_TPREL_G0:
|
|
return EncodedValue & ~(1u << 30);
|
|
default:
|
|
// Nothing to do for an unsigned fixup.
|
|
return EncodedValue;
|
|
}
|
|
|
|
llvm_unreachable("Should have returned by now");
|
|
}
|
|
|
|
unsigned
|
|
AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI,
|
|
unsigned EncodedValue) const {
|
|
// The Ra field of SMULH and UMULH is unused: it should be assembled as 31
|
|
// (i.e. all bits 1) but is ignored by the processor.
|
|
EncodedValue |= 0x1f << 10;
|
|
return EncodedValue;
|
|
}
|
|
|
|
MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
|
|
const MCRegisterInfo &MRI,
|
|
const MCSubtargetInfo &STI,
|
|
MCContext &Ctx) {
|
|
return new AArch64MCCodeEmitter(Ctx);
|
|
}
|
|
|
|
void AArch64MCCodeEmitter::
|
|
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
if (MI.getOpcode() == AArch64::TLSDESCCALL) {
|
|
// This is a directive which applies an R_AARCH64_TLSDESC_CALL to the
|
|
// following (BLR) instruction. It doesn't emit any code itself so it
|
|
// doesn't go through the normal TableGenerated channels.
|
|
MCFixupKind Fixup = MCFixupKind(AArch64::fixup_a64_tlsdesc_call);
|
|
const MCExpr *Expr;
|
|
Expr = AArch64MCExpr::CreateTLSDesc(MI.getOperand(0).getExpr(), Ctx);
|
|
Fixups.push_back(MCFixup::Create(0, Expr, Fixup));
|
|
return;
|
|
}
|
|
|
|
uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
|
|
|
|
EmitInstruction(Binary, OS);
|
|
}
|
|
|
|
|
|
#include "AArch64GenMCCodeEmitter.inc"
|