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https://github.com/c64scene-ar/llvm-6502.git
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054c1f6cb6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4328 91177308-0d34-0410-b5e6-96231b3b80d8
355 lines
13 KiB
C++
355 lines
13 KiB
C++
//===-- llvm/CodeGen/InstrSelectionSupport.h --------------------*- C++ -*-===//
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//
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// Target-independent instruction selection code. See SparcInstrSelection.cpp
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// for usage.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_INSTR_SELECTION_SUPPORT_H
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#define LLVM_CODEGEN_INSTR_SELECTION_SUPPORT_H
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#include "llvm/Instruction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "Support/DataTypes.h"
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class InstructionNode;
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class TargetMachine;
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//---------------------------------------------------------------------------
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// Function GetConstantValueAsUnsignedInt
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// Function GetConstantValueAsSignedInt
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//
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// Convenience functions to get the value of an integer constant, for an
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// appropriate integer or non-integer type that can be held in a signed
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// or unsigned integer respectively. The type of the argument must be
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// the following:
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// Signed or unsigned integer
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// Boolean
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// Pointer
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//
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// isValidConstant is set to true if a valid constant was found.
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//---------------------------------------------------------------------------
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uint64_t GetConstantValueAsUnsignedInt (const Value *V,
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bool &isValidConstant);
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int64_t GetConstantValueAsSignedInt (const Value *V,
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bool &isValidConstant);
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//---------------------------------------------------------------------------
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// Function: GetMemInstArgs
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//
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// Purpose:
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// Get the pointer value and the index vector for a memory operation
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// (GetElementPtr, Load, or Store). If all indices of the given memory
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// operation are constant, fold in constant indices in a chain of
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// preceding GetElementPtr instructions (if any), and return the
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// pointer value of the first instruction in the chain.
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// All folded instructions are marked so no code is generated for them.
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//
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// Return values:
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// Returns the pointer Value to use.
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// Returns the resulting IndexVector in idxVec.
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// Returns true/false in allConstantIndices if all indices are/aren't const.
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//---------------------------------------------------------------------------
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Value* GetMemInstArgs (InstructionNode* memInstrNode,
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std::vector<Value*>& idxVec,
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bool& allConstantIndices);
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//------------------------------------------------------------------------
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// Function Set2OperandsFromInstr
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// Function Set3OperandsFromInstr
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//
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// Purpose:
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//
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// For the common case of 2- and 3-operand arithmetic/logical instructions,
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// set the m/c instr. operands directly from the VM instruction's operands.
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// Check whether the first or second operand is 0 and can use a dedicated
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// "0" register.
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// Check whether the second operand should use an immediate field or register.
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// (First and third operands are never immediates for such instructions.)
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//
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// Arguments:
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// canDiscardResult: Specifies that the result operand can be discarded
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// by using the dedicated "0"
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//
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// op1position, op2position and resultPosition: Specify in which position
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// in the machine instruction the 3 operands (arg1, arg2
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// and result) should go.
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//
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// RETURN VALUE: unsigned int flags, where
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// flags & 0x01 => operand 1 is constant and needs a register
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// flags & 0x02 => operand 2 is constant and needs a register
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//------------------------------------------------------------------------
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void Set2OperandsFromInstr (MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& targetMachine,
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bool canDiscardResult = false,
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int op1Position = 0,
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int resultPosition = 1);
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void Set3OperandsFromInstr (MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& targetMachine,
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bool canDiscardResult = false,
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int op1Position = 0,
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int op2Position = 1,
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int resultPosition = 2);
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//------------------------------------------------------------------------
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// Common machine instruction operand combinations
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// to simplify code generation.
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//------------------------------------------------------------------------
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inline MachineInstr*
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Create1OperandInstr(MachineOpCode opCode, Value* argVal1)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1);
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return M;
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}
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inline MachineInstr*
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Create1OperandInstr_UImmed(MachineOpCode opCode, unsigned int unextendedImmed)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandConst(0, MachineOperand::MO_UnextendedImmed,
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unextendedImmed);
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return M;
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}
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inline MachineInstr*
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Create1OperandInstr_SImmed(MachineOpCode opCode, int signExtendedImmed)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandConst(0, MachineOperand::MO_SignExtendedImmed,
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signExtendedImmed);
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return M;
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}
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inline MachineInstr*
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Create1OperandInstr_Addr(MachineOpCode opCode, Value* label)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp, label);
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return M;
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}
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inline MachineInstr*
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Create2OperandInstr(MachineOpCode opCode, Value* argVal1, Value* argVal2)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1);
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, argVal2);
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return M;
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}
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inline MachineInstr*
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Create2OperandInstr(MachineOpCode opCode,
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Value* argVal1, MachineOperand::MachineOperandType type1,
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Value* argVal2, MachineOperand::MachineOperandType type2)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, type1, argVal1);
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M->SetMachineOperandVal(1, type2, argVal2);
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return M;
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}
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inline MachineInstr*
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Create2OperandInstr_UImmed(MachineOpCode opCode,
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unsigned int unextendedImmed, Value* argVal2)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandConst(0, MachineOperand::MO_UnextendedImmed,
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unextendedImmed);
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, argVal2);
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return M;
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}
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inline MachineInstr*
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Create2OperandInstr_SImmed(MachineOpCode opCode,
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int signExtendedImmed, Value* argVal2)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandConst(0, MachineOperand::MO_SignExtendedImmed,
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signExtendedImmed);
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, argVal2);
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return M;
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}
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inline MachineInstr*
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Create2OperandInstr_Addr(MachineOpCode opCode,
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Value* label, Value* argVal2)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp, label);
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, argVal2);
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return M;
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}
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inline MachineInstr*
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Create2OperandInstr_Reg(MachineOpCode opCode,
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Value* argVal1, unsigned int regNum)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1);
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M->SetMachineOperandReg(1, regNum);
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return M;
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}
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inline MachineInstr*
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Create2OperandInstr_Reg(MachineOpCode opCode,
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unsigned int regNum1, unsigned int regNum2)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandReg(0, regNum1);
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M->SetMachineOperandReg(1, regNum2);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr(MachineOpCode opCode,
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Value* argVal1, MachineOperand::MachineOperandType type1,
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Value* argVal2, MachineOperand::MachineOperandType type2,
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Value* argVal3, MachineOperand::MachineOperandType type3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, type1, argVal1);
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M->SetMachineOperandVal(1, type2, argVal2);
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M->SetMachineOperandVal(2, type3, argVal3);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr(MachineOpCode opCode, Value* argVal1,
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Value* argVal2, Value* argVal3)
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{
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return Create3OperandInstr(opCode,
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argVal1, MachineOperand::MO_VirtualRegister,
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argVal2, MachineOperand::MO_VirtualRegister,
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argVal3, MachineOperand::MO_VirtualRegister);
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}
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inline MachineInstr*
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Create3OperandInstr_UImmed(MachineOpCode opCode, Value* argVal1,
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unsigned int unextendedImmed, Value* argVal3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1);
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M->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed,
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unextendedImmed);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, argVal3);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr_SImmed(MachineOpCode opCode, Value* argVal1,
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int signExtendedImmed, Value* argVal3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1);
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M->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
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signExtendedImmed);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, argVal3);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr_Addr(MachineOpCode opCode, Value* argVal1,
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Value* label, Value* argVal3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1);
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M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp, label);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, argVal3);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr_Reg(MachineOpCode opCode, Value* argVal1,
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unsigned int regNum, Value* argVal3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1);
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M->SetMachineOperandReg(1, regNum);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, argVal3);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr_Reg(MachineOpCode opCode, unsigned int regNum1,
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unsigned int regNum2, Value* argVal3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandReg(0, regNum1);
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M->SetMachineOperandReg(1, regNum2);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, argVal3);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr_Reg(MachineOpCode opCode, unsigned int regNum1,
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unsigned int regNum2, unsigned int regNum3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandReg(0, regNum1);
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M->SetMachineOperandReg(1, regNum2);
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M->SetMachineOperandReg(2, regNum3);
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return M;
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}
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//---------------------------------------------------------------------------
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// Function: ChooseRegOrImmed
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//
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// Purpose:
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//
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//---------------------------------------------------------------------------
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MachineOperand::MachineOperandType ChooseRegOrImmed(
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Value* val,
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MachineOpCode opCode,
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const TargetMachine& targetMachine,
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bool canUseImmed,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue);
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MachineOperand::MachineOperandType ChooseRegOrImmed(int64_t intValue,
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bool isSigned,
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MachineOpCode opCode,
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const TargetMachine& target,
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bool canUseImmed,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue);
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//---------------------------------------------------------------------------
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// Function: FixConstantOperandsForInstr
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//
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// Purpose:
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// Special handling for constant operands of a machine instruction
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// -- if the constant is 0, use the hardwired 0 register, if any;
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// -- if the constant fits in the IMMEDIATE field, use that field;
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// -- else create instructions to put the constant into a register, either
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// directly or by loading explicitly from the constant pool.
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//
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// In the first 2 cases, the operand of `minstr' is modified in place.
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// Returns a vector of machine instructions generated for operands that
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// fall under case 3; these must be inserted before `minstr'.
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//---------------------------------------------------------------------------
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std::vector<MachineInstr*> FixConstantOperandsForInstr (Instruction* vmInstr,
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MachineInstr* minstr,
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TargetMachine& target);
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#endif
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