JF Bastien 9994b911f4 Targets: commonize some stack realignment code ... This patch does the following: * Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`. * Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute. Multiple targets duplicated the same `needsStackRealignment` code: - Aarch64. - ARM. - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has. - PowerPC. - WebAssembly. - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has. The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects: - AMDGPU - BPF - CppBackend - MSP430 - NVPTX - Sparc - SystemZ - XCore - Out-of-tree targets This is a breaking change! `make check` passes. The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation. `needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242727 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-20 22:51:32 +00:00
..
AArch64	AArch64: Add aditional Cyclone macroop fusion opportunities	2015-07-20 22:34:47 +00:00
AMDGPU	AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops	2015-07-20 14:28:41 +00:00
ARM	[ARM] Refactor the prologue/epilogue emission to be more robust.	2015-07-20 21:42:14 +00:00
BPF
CPP
Generic	Targets: commonize some stack realignment code	2015-07-20 22:51:32 +00:00
Hexagon	[Hexagon] Generate MUX from conditional transfers when dot-new not possible	2015-07-20 21:23:25 +00:00
Inputs
Mips
MIR	MIR Serialization: Initial serialization of machine constant pools.	2015-07-20 20:51:18 +00:00
MSP430
NVPTX	[NVPTX] make load on global readonly memory to use ldg	2015-07-20 21:28:54 +00:00
PowerPC	Add missing test for r242296 (vec_sld)	2015-07-20 15:43:21 +00:00
SPARC
SystemZ
Thumb	[ARM] Refactor the prologue/epilogue emission to be more robust.	2015-07-20 21:42:14 +00:00
Thumb2	ARM: Add scheduling information for LDRLIT instructions to swift scheduling model	2015-07-17 23:18:26 +00:00
WebAssembly
WinEH
X86	[ImplicitNullChecks] Work with implicit defs.	2015-07-20 20:31:39 +00:00
XCore