llvm-6502/lib/Target/Sparc
David Blaikie 0187e7a9ba DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-16 20:34:27 +00:00
..
MCTargetDesc
TargetInfo
CMakeLists.txt [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. 2013-06-08 15:32:59 +00:00
DelaySlotFiller.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:35:25 +00:00
LLVMBuild.txt Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
Makefile
README.txt Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
Sparc.h [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. 2013-06-08 15:32:59 +00:00
Sparc.td Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
SparcAsmPrinter.cpp DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 2013-06-16 20:34:27 +00:00
SparcCallingConv.td Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
SparcFrameLowering.cpp Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
SparcFrameLowering.h Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
SparcInstr64Bit.td Remember the anyext patterns. 2013-06-07 22:59:29 +00:00
SparcInstrFormats.td Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
SparcInstrInfo.cpp DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 2013-06-16 20:34:27 +00:00
SparcInstrInfo.h DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 2013-06-16 20:34:27 +00:00
SparcInstrInfo.td [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. 2013-06-08 15:32:59 +00:00
SparcISelDAGToDAG.cpp Cache the TargetLowering info object as a pointer. 2013-06-06 00:43:09 +00:00
SparcISelLowering.cpp [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. 2013-06-08 15:32:59 +00:00
SparcISelLowering.h Sparc: Add support for indirect branch and blockaddress in Sparc backend. 2013-06-03 05:58:33 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcRegisterInfo.cpp Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:35:25 +00:00
SparcRegisterInfo.h Don't cache the instruction and register info from the TargetMachine, because 2013-06-07 20:35:25 +00:00
SparcRegisterInfo.td Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
SparcSubtarget.h Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
SparcTargetMachine.cpp [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. 2013-06-08 15:32:59 +00:00
SparcTargetMachine.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Implement JIT support

* Use %g0 directly to materialize 0. No instruction is required.