mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
380417ac84
E.g. Lower an interleaved load:
%wide.vec = load <8 x i32>, <8 x i32>* %ptr
%v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>
%v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>
into:
%ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
%vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
%vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1
E.g. Lower an interleaved store:
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr
into:
%sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
%sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
%sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
Differential Revision: http://reviews.llvm.org/D10533
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240754 91177308-0d34-0410-b5e6-96231b3b80d8
198 lines
10 KiB
LLVM
198 lines
10 KiB
LLVM
; RUN: llc -march=aarch64 -aarch64-neon-syntax=generic -lower-interleaved-accesses=true < %s | FileCheck %s
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; CHECK-LABEL: load_factor2:
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; CHECK: ld2 { v0.8b, v1.8b }, [x0]
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define <8 x i8> @load_factor2(<16 x i8>* %ptr) {
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%wide.vec = load <16 x i8>, <16 x i8>* %ptr, align 4
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%strided.v0 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%strided.v1 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%add = add nsw <8 x i8> %strided.v0, %strided.v1
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ret <8 x i8> %add
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}
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; CHECK-LABEL: load_factor3:
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; CHECK: ld3 { v0.4s, v1.4s, v2.4s }, [x0]
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define <4 x i32> @load_factor3(i32* %ptr) {
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%base = bitcast i32* %ptr to <12 x i32>*
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%wide.vec = load <12 x i32>, <12 x i32>* %base, align 4
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%strided.v2 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
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%strided.v1 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
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%add = add nsw <4 x i32> %strided.v2, %strided.v1
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ret <4 x i32> %add
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}
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; CHECK-LABEL: load_factor4:
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; CHECK: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0]
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define <4 x i32> @load_factor4(i32* %ptr) {
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%base = bitcast i32* %ptr to <16 x i32>*
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%wide.vec = load <16 x i32>, <16 x i32>* %base, align 4
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%strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
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%strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
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%add = add nsw <4 x i32> %strided.v0, %strided.v2
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ret <4 x i32> %add
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}
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; CHECK-LABEL: store_factor2:
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; CHECK: st2 { v0.8b, v1.8b }, [x0]
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define void @store_factor2(<16 x i8>* %ptr, <8 x i8> %v0, <8 x i8> %v1) {
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%interleaved.vec = shufflevector <8 x i8> %v0, <8 x i8> %v1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
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store <16 x i8> %interleaved.vec, <16 x i8>* %ptr, align 4
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ret void
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}
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; CHECK-LABEL: store_factor3:
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; CHECK: st3 { v0.4s, v1.4s, v2.4s }, [x0]
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define void @store_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
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%base = bitcast i32* %ptr to <12 x i32>*
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%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%v2_u = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_u, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
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store <12 x i32> %interleaved.vec, <12 x i32>* %base, align 4
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ret void
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}
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; CHECK-LABEL: store_factor4:
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; CHECK: st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0]
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define void @store_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
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%base = bitcast i32* %ptr to <16 x i32>*
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%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%v2_v3 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_v3, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
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store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4
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ret void
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}
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; The following cases test that interleaved access of pointer vectors can be
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; matched to ldN/stN instruction.
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; CHECK-LABEL: load_ptrvec_factor2:
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; CHECK: ld2 { v0.2d, v1.2d }, [x0]
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define <2 x i32*> @load_ptrvec_factor2(i32** %ptr) {
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%base = bitcast i32** %ptr to <4 x i32*>*
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%wide.vec = load <4 x i32*>, <4 x i32*>* %base, align 4
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%strided.v0 = shufflevector <4 x i32*> %wide.vec, <4 x i32*> undef, <2 x i32> <i32 0, i32 2>
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ret <2 x i32*> %strided.v0
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}
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; CHECK-LABEL: load_ptrvec_factor3:
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; CHECK: ld3 { v0.2d, v1.2d, v2.2d }, [x0]
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define void @load_ptrvec_factor3(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) {
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%base = bitcast i32** %ptr to <6 x i32*>*
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%wide.vec = load <6 x i32*>, <6 x i32*>* %base, align 4
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%strided.v2 = shufflevector <6 x i32*> %wide.vec, <6 x i32*> undef, <2 x i32> <i32 2, i32 5>
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store <2 x i32*> %strided.v2, <2 x i32*>* %ptr1
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%strided.v1 = shufflevector <6 x i32*> %wide.vec, <6 x i32*> undef, <2 x i32> <i32 1, i32 4>
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store <2 x i32*> %strided.v1, <2 x i32*>* %ptr2
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ret void
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}
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; CHECK-LABEL: load_ptrvec_factor4:
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; CHECK: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
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define void @load_ptrvec_factor4(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) {
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%base = bitcast i32** %ptr to <8 x i32*>*
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%wide.vec = load <8 x i32*>, <8 x i32*>* %base, align 4
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%strided.v1 = shufflevector <8 x i32*> %wide.vec, <8 x i32*> undef, <2 x i32> <i32 1, i32 5>
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%strided.v3 = shufflevector <8 x i32*> %wide.vec, <8 x i32*> undef, <2 x i32> <i32 3, i32 7>
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store <2 x i32*> %strided.v1, <2 x i32*>* %ptr1
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store <2 x i32*> %strided.v3, <2 x i32*>* %ptr2
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ret void
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}
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; CHECK-LABEL: store_ptrvec_factor2:
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; CHECK: st2 { v0.2d, v1.2d }, [x0]
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define void @store_ptrvec_factor2(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1) {
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%base = bitcast i32** %ptr to <4 x i32*>*
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%interleaved.vec = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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store <4 x i32*> %interleaved.vec, <4 x i32*>* %base, align 4
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ret void
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}
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; CHECK-LABEL: store_ptrvec_factor3:
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; CHECK: st3 { v0.2d, v1.2d, v2.2d }, [x0]
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define void @store_ptrvec_factor3(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2) {
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%base = bitcast i32** %ptr to <6 x i32*>*
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%v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%v2_u = shufflevector <2 x i32*> %v2, <2 x i32*> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%interleaved.vec = shufflevector <4 x i32*> %v0_v1, <4 x i32*> %v2_u, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
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store <6 x i32*> %interleaved.vec, <6 x i32*>* %base, align 4
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ret void
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}
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; CHECK-LABEL: store_ptrvec_factor4:
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; CHECK: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
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define void @store_ptrvec_factor4(i32* %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2, <2 x i32*> %v3) {
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%base = bitcast i32* %ptr to <8 x i32*>*
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%v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%v2_v3 = shufflevector <2 x i32*> %v2, <2 x i32*> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%interleaved.vec = shufflevector <4 x i32*> %v0_v1, <4 x i32*> %v2_v3, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
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store <8 x i32*> %interleaved.vec, <8 x i32*>* %base, align 4
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ret void
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}
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; Following cases check that shuffle maskes with undef indices can be matched
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; into ldN/stN instruction.
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; CHECK-LABEL: load_undef_mask_factor2:
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; CHECK: ld2 { v0.4s, v1.4s }, [x0]
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define <4 x i32> @load_undef_mask_factor2(i32* %ptr) {
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%base = bitcast i32* %ptr to <8 x i32>*
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%wide.vec = load <8 x i32>, <8 x i32>* %base, align 4
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%strided.v0 = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 6>
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%strided.v1 = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 7>
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%add = add nsw <4 x i32> %strided.v0, %strided.v1
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ret <4 x i32> %add
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}
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; CHECK-LABEL: load_undef_mask_factor3:
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; CHECK: ld3 { v0.4s, v1.4s, v2.4s }, [x0]
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define <4 x i32> @load_undef_mask_factor3(i32* %ptr) {
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%base = bitcast i32* %ptr to <12 x i32>*
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%wide.vec = load <12 x i32>, <12 x i32>* %base, align 4
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%strided.v2 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>
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%strided.v1 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
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%add = add nsw <4 x i32> %strided.v2, %strided.v1
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ret <4 x i32> %add
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}
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; CHECK-LABEL: load_undef_mask_factor4:
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; CHECK: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0]
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define <4 x i32> @load_undef_mask_factor4(i32* %ptr) {
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%base = bitcast i32* %ptr to <16 x i32>*
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%wide.vec = load <16 x i32>, <16 x i32>* %base, align 4
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%strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 undef, i32 undef>
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%strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 undef, i32 undef>
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%add = add nsw <4 x i32> %strided.v0, %strided.v2
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ret <4 x i32> %add
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}
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; CHECK-LABEL: store_undef_mask_factor2:
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; CHECK: st2 { v0.4s, v1.4s }, [x0]
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define void @store_undef_mask_factor2(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1) {
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%base = bitcast i32* %ptr to <8 x i32>*
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%interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7>
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store <8 x i32> %interleaved.vec, <8 x i32>* %base, align 4
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ret void
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}
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; CHECK-LABEL: store_undef_mask_factor3:
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; CHECK: st3 { v0.4s, v1.4s, v2.4s }, [x0]
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define void @store_undef_mask_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
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%base = bitcast i32* %ptr to <12 x i32>*
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%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%v2_u = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_u, <12 x i32> <i32 0, i32 4, i32 undef, i32 1, i32 undef, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
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store <12 x i32> %interleaved.vec, <12 x i32>* %base, align 4
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ret void
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}
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; CHECK-LABEL: store_undef_mask_factor4:
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; CHECK: st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0]
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define void @store_undef_mask_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
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%base = bitcast i32* %ptr to <16 x i32>*
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%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%v2_v3 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_v3, <16 x i32> <i32 0, i32 4, i32 8, i32 undef, i32 undef, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
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store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4
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ret void
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}
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