mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
9217916725
"Fix the MachineScheduler's logic for updating ready times for in-order. Now the scheduler updates a node's ready time as soon as it is scheduled, before releasing dependent nodes." This fix was only made in one variant of the ScheduleDAGMI driver. Francois de Ferriere reported the issue in the other bit of code where it was also needed. I never got around to coming up with a test case, but it's an obvious fix that shouldn't be delayed any longer. I'll try to refactor this code a little better. I did verify performance on a wide variety of targets and saw no negative impact with this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233366 91177308-0d34-0410-b5e6-96231b3b80d8
130 lines
4.8 KiB
LLVM
130 lines
4.8 KiB
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-NOOPT
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; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-OPT
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; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-NOOPT
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; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-OPT
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define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: bar:
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; CHECK: add.2d v[[REG:[0-9]+]], v0, v1
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; CHECK: add d[[REG3:[0-9]+]], d[[REG]], d1
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; CHECK: sub d[[REG2:[0-9]+]], d[[REG]], d1
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; Without advanced copy optimization, we end up with cross register
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; banks copies that cannot be coalesced.
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; CHECK-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]]
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; With advanced copy optimization, we end up with just one copy
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; to insert the computed high part into the V register.
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; CHECK-OPT-NOT: fmov
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; CHECK: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]
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; CHECK-NOOPT: fmov d0, [[COPY_REG3]]
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; CHECK-OPT-NOT: fmov
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; CHECK: ins.d v0[1], [[COPY_REG2]]
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; CHECK-NEXT: ret
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;
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; GENERIC-LABEL: bar:
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; GENERIC: add v[[REG:[0-9]+]].2d, v0.2d, v1.2d
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; GENERIC: add d[[REG3:[0-9]+]], d[[REG]], d1
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; GENERIC: sub d[[REG2:[0-9]+]], d[[REG]], d1
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; GENERIC-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]]
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; GENERIC-OPT-NOT: fmov
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; GENERIC: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]
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; GENERIC-NOOPT: fmov d0, [[COPY_REG3]]
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; GENERIC-OPT-NOT: fmov
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; GENERIC: ins v0.d[1], [[COPY_REG2]]
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; GENERIC-NEXT: ret
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%add = add <2 x i64> %a, %b
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%vgetq_lane = extractelement <2 x i64> %add, i32 0
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%vgetq_lane2 = extractelement <2 x i64> %b, i32 0
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%add3 = add i64 %vgetq_lane, %vgetq_lane2
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%sub = sub i64 %vgetq_lane, %vgetq_lane2
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%vecinit = insertelement <2 x i64> undef, i64 %add3, i32 0
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%vecinit8 = insertelement <2 x i64> %vecinit, i64 %sub, i32 1
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ret <2 x i64> %vecinit8
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}
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define double @subdd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: subdd_su64:
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; CHECK: sub d0, d1, d0
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; CHECK-NEXT: ret
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; GENERIC-LABEL: subdd_su64:
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; GENERIC: sub d0, d1, d0
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; GENERIC-NEXT: ret
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%vecext = extractelement <2 x i64> %a, i32 0
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%vecext1 = extractelement <2 x i64> %b, i32 0
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%sub.i = sub nsw i64 %vecext1, %vecext
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%retval = bitcast i64 %sub.i to double
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ret double %retval
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}
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define double @vaddd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: vaddd_su64:
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; CHECK: add d0, d1, d0
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; CHECK-NEXT: ret
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; GENERIC-LABEL: vaddd_su64:
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; GENERIC: add d0, d1, d0
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; GENERIC-NEXT: ret
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%vecext = extractelement <2 x i64> %a, i32 0
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%vecext1 = extractelement <2 x i64> %b, i32 0
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%add.i = add nsw i64 %vecext1, %vecext
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%retval = bitcast i64 %add.i to double
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ret double %retval
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}
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; sub MI doesn't access dsub register.
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define double @add_sub_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: add_sub_su64:
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; CHECK: add d0, d1, d0
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; CHECK: sub d0, {{d[0-9]+}}, d0
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; CHECK-NEXT: ret
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; GENERIC-LABEL: add_sub_su64:
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; GENERIC: add d0, d1, d0
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; GENERIC: sub d0, {{d[0-9]+}}, d0
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; GENERIC-NEXT: ret
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%vecext = extractelement <2 x i64> %a, i32 0
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%vecext1 = extractelement <2 x i64> %b, i32 0
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%add.i = add i64 %vecext1, %vecext
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%sub.i = sub i64 0, %add.i
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%retval = bitcast i64 %sub.i to double
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ret double %retval
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}
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define double @and_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: and_su64:
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; CHECK: and.8b v0, v1, v0
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; CHECK-NEXT: ret
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; GENERIC-LABEL: and_su64:
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; GENERIC: and v0.8b, v1.8b, v0.8b
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; GENERIC-NEXT: ret
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%vecext = extractelement <2 x i64> %a, i32 0
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%vecext1 = extractelement <2 x i64> %b, i32 0
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%or.i = and i64 %vecext1, %vecext
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%retval = bitcast i64 %or.i to double
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ret double %retval
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}
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define double @orr_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: orr_su64:
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; CHECK: orr.8b v0, v1, v0
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; CHECK-NEXT: ret
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; GENERIC-LABEL: orr_su64:
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; GENERIC: orr v0.8b, v1.8b, v0.8b
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; GENERIC-NEXT: ret
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%vecext = extractelement <2 x i64> %a, i32 0
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%vecext1 = extractelement <2 x i64> %b, i32 0
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%or.i = or i64 %vecext1, %vecext
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%retval = bitcast i64 %or.i to double
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ret double %retval
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}
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define double @xorr_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: xorr_su64:
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; CHECK: eor.8b v0, v1, v0
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; CHECK-NEXT: ret
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; GENERIC-LABEL: xorr_su64:
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; GENERIC: eor v0.8b, v1.8b, v0.8b
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; GENERIC-NEXT: ret
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%vecext = extractelement <2 x i64> %a, i32 0
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%vecext1 = extractelement <2 x i64> %b, i32 0
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%xor.i = xor i64 %vecext1, %vecext
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%retval = bitcast i64 %xor.i to double
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ret double %retval
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}
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