llvm-6502/test/CodeGen/AArch64/arm64-long-shift.ll
Tim Northover 29f94c7201 AArch64/ARM64: move ARM64 into AArch64's place
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.

"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.

This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 12:50:23 +00:00

60 lines
2.1 KiB
LLVM

; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
define i128 @shl(i128 %r, i128 %s) nounwind readnone {
; CHECK-LABEL: shl:
; CHECK: lsl [[XREG_0:x[0-9]+]], x1, x2
; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
; CHECK-NEXT: lsr [[XREG_3:x[0-9]+]], x0, [[XREG_2]]
; CHECK-NEXT: orr [[XREG_6:x[0-9]+]], [[XREG_3]], [[XREG_0]]
; CHECK-NEXT: sub [[XREG_4:x[0-9]+]], x2, #64
; CHECK-NEXT: lsl [[XREG_5:x[0-9]+]], x0, [[XREG_4]]
; CHECK-NEXT: cmp [[XREG_4]], #0
; CHECK-NEXT: csel x1, [[XREG_5]], [[XREG_6]], ge
; CHECK-NEXT: lsl [[SMALLSHIFT_LO:x[0-9]+]], x0, x2
; CHECK-NEXT: csel x0, xzr, [[SMALLSHIFT_LO]], ge
; CHECK-NEXT: ret
%shl = shl i128 %r, %s
ret i128 %shl
}
define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
; CHECK-LABEL: ashr:
; CHECK: lsr [[XREG_0:x[0-9]+]], x0, x2
; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
; CHECK-NEXT: lsl [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
; CHECK-NEXT: asr [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
; CHECK-NEXT: cmp [[XREG_5]], #0
; CHECK-NEXT: csel x0, [[XREG_6]], [[XREG_4]], ge
; CHECK-NEXT: asr [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
; CHECK-NEXT: asr [[BIGSHIFT_HI:x[0-9]+]], x1, #63
; CHECK-NEXT: csel x1, [[BIGSHIFT_HI]], [[SMALLSHIFT_HI]], ge
; CHECK-NEXT: ret
%shr = ashr i128 %r, %s
ret i128 %shr
}
define i128 @lshr(i128 %r, i128 %s) nounwind readnone {
; CHECK-LABEL: lshr:
; CHECK: lsr [[XREG_0:x[0-9]+]], x0, x2
; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
; CHECK-NEXT: lsl [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
; CHECK-NEXT: lsr [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
; CHECK-NEXT: cmp [[XREG_5]], #0
; CHECK-NEXT: csel x0, [[XREG_6]], [[XREG_4]], ge
; CHECK-NEXT: lsr [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
; CHECK-NEXT: csel x1, xzr, [[SMALLSHIFT_HI]], ge
; CHECK-NEXT: ret
%shr = lshr i128 %r, %s
ret i128 %shr
}