mirror of
https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
176 lines
7.5 KiB
LLVM
176 lines
7.5 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
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; FIXME: We should not generate ld/st for such register spill/fill, because the
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; test case seems very simple and the register pressure is not high. If the
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; spill/fill algorithm is optimized, this test case may not be triggered. And
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; then we can delete it.
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define i32 @spill.DPairReg(i32* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.DPairReg:
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; CHECK: ld2 { v{{[0-9]+}}.2s, v{{[0-9]+}}.2s }, [{{x[0-9]+|sp}}]
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; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
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; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2.v2i32.p0i32(i32* %arg1)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <2 x i32>, <2 x i32> } %vld, 0
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%res = extractelement <2 x i32> %vld.extract, i32 1
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ret i32 %res
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}
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define i16 @spill.DTripleReg(i16* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.DTripleReg:
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; CHECK: ld3 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}]
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; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
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; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0i16(i16* %arg1)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } %vld, 0
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%res = extractelement <4 x i16> %vld.extract, i32 1
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ret i16 %res
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}
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define i16 @spill.DQuadReg(i16* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.DQuadReg:
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; CHECK: ld4 { v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h }, [{{x[0-9]+|sp}}]
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; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
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; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0i16(i16* %arg1)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %vld, 0
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%res = extractelement <4 x i16> %vld.extract, i32 0
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ret i16 %res
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}
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define i32 @spill.QPairReg(i32* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.QPairReg:
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; CHECK: ld2 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}]
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; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
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; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i32(i32* %arg1)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <4 x i32>, <4 x i32> } %vld, 0
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%res = extractelement <4 x i32> %vld.extract, i32 1
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ret i32 %res
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}
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define float @spill.QTripleReg(float* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.QTripleReg:
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; CHECK: ld3 { v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s }, [{{x[0-9]+|sp}}]
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; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
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; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
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entry:
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%vld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p0f32(float* %arg1)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld3.extract = extractvalue { <4 x float>, <4 x float>, <4 x float> } %vld3, 0
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%res = extractelement <4 x float> %vld3.extract, i32 1
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ret float %res
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}
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define i8 @spill.QQuadReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.QQuadReg:
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; CHECK: ld4 { v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b }, [{{x[0-9]+|sp}}]
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; CHECK: st1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
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; CHECK: ld1 { v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d }, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(i8* %arg1)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vld, 0
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%res = extractelement <16 x i8> %vld.extract, i32 1
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ret i8 %res
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}
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declare { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2.v2i32.p0i32(i32*)
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declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0i16(i16*)
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declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0i16(i16*)
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declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i32(i32*)
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declare { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p0f32(float*)
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declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(i8*)
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declare void @foo()
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; FIXME: We should not generate ld/st for such register spill/fill, because the
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; test case seems very simple and the register pressure is not high. If the
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; spill/fill algorithm is optimized, this test case may not be triggered. And
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; then we can delete it.
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; check the spill for Register Class QPair_with_qsub_0_in_FPR128Lo
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define <8 x i16> @test_2xFPR128Lo(i64 %got, i64* %ptr, <1 x i64> %a) {
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tail call void @llvm.aarch64.neon.st2lane.v1i64.p0i64(<1 x i64> zeroinitializer, <1 x i64> zeroinitializer, i64 0, i64* %ptr)
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tail call void @foo()
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%sv = shufflevector <1 x i64> zeroinitializer, <1 x i64> %a, <2 x i32> <i32 0, i32 1>
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%1 = bitcast <2 x i64> %sv to <8 x i16>
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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%3 = mul <8 x i16> %2, %2
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ret <8 x i16> %3
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}
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; check the spill for Register Class QTriple_with_qsub_0_in_FPR128Lo
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define <8 x i16> @test_3xFPR128Lo(i64 %got, i64* %ptr, <1 x i64> %a) {
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tail call void @llvm.aarch64.neon.st3lane.v1i64.p0i64(<1 x i64> zeroinitializer, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, i64 0, i64* %ptr)
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tail call void @foo()
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%sv = shufflevector <1 x i64> zeroinitializer, <1 x i64> %a, <2 x i32> <i32 0, i32 1>
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%1 = bitcast <2 x i64> %sv to <8 x i16>
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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%3 = mul <8 x i16> %2, %2
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ret <8 x i16> %3
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}
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; check the spill for Register Class QQuad_with_qsub_0_in_FPR128Lo
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define <8 x i16> @test_4xFPR128Lo(i64 %got, i64* %ptr, <1 x i64> %a) {
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tail call void @llvm.aarch64.neon.st4lane.v1i64.p0i64(<1 x i64> zeroinitializer, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, i64 0, i64* %ptr)
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tail call void @foo()
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%sv = shufflevector <1 x i64> zeroinitializer, <1 x i64> %a, <2 x i32> <i32 0, i32 1>
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%1 = bitcast <2 x i64> %sv to <8 x i16>
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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%3 = mul <8 x i16> %2, %2
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ret <8 x i16> %3
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}
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declare void @llvm.aarch64.neon.st2lane.v1i64.p0i64(<1 x i64>, <1 x i64>, i64, i64*)
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declare void @llvm.aarch64.neon.st3lane.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, i64, i64*)
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declare void @llvm.aarch64.neon.st4lane.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i64, i64*)
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