mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
4a3cd42601
This adds new node types for each intrinsic.
For instance, for addv, we have AArch64ISD::UADDV, such that:
(v4i32 (uaddv ...))
is the same as
(v4i32 (scalar_to_vector (i32 (int_aarch64_neon_uaddv ...))))
that is,
(v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
(i32 (int_aarch64_neon_uaddv ...)), ssub)
In a combine, we transform all such across-vector-lanes intrinsics to:
(i32 (extract_vector_elt (uaddv ...), 0))
This has one big advantage: by making the extract_element explicit, we
enable the existing patterns for lane-aware instructions to fire.
This lets us avoid needlessly going through the GPRs. Consider:
uint32x4_t test_mul(uint32x4_t a, uint32x4_t b) {
return vmulq_n_u32(a, vaddvq_u32(b));
}
We now generate:
addv.4s s1, v1
mul.4s v0, v0, v1[0]
instead of the previous:
addv.4s s1, v1
fmov w8, s1
dup.4s v1, w8
mul.4s v0, v1, v0
rdar://20044838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231840 91177308-0d34-0410-b5e6-96231b3b80d8
145 lines
4.5 KiB
LLVM
145 lines
4.5 KiB
LLVM
; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false < %s | FileCheck %s
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define signext i8 @test_vminv_s8(<8 x i8> %a1) {
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; CHECK: test_vminv_s8
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; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a1)
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%0 = trunc i32 %vminv.i to i8
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ret i8 %0
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}
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define signext i16 @test_vminv_s16(<4 x i16> %a1) {
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; CHECK: test_vminv_s16
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; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a1)
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%0 = trunc i32 %vminv.i to i16
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ret i16 %0
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}
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define i32 @test_vminv_s32(<2 x i32> %a1) {
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; CHECK: test_vminv_s32
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; 2 x i32 is not supported by the ISA, thus, this is a special case
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; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v0, v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a1)
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ret i32 %vminv.i
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}
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define signext i8 @test_vminvq_s8(<16 x i8> %a1) {
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; CHECK: test_vminvq_s8
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; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a1)
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%0 = trunc i32 %vminv.i to i8
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ret i8 %0
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}
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define signext i16 @test_vminvq_s16(<8 x i16> %a1) {
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; CHECK: test_vminvq_s16
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; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a1)
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%0 = trunc i32 %vminv.i to i16
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ret i16 %0
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}
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define i32 @test_vminvq_s32(<4 x i32> %a1) {
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; CHECK: test_vminvq_s32
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; CHECK: sminv.4s [[REGNUM:s[0-9]+]], v0
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; CHECK-NEXT: fmov w0, [[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a1)
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ret i32 %vminv.i
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}
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define <8 x i8> @test_vminv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
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; CHECK-LABEL: test_vminv_s8_used_by_laneop:
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; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a2)
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%1 = trunc i32 %0 to i8
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%2 = insertelement <8 x i8> %a1, i8 %1, i32 3
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ret <8 x i8> %2
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}
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define <4 x i16> @test_vminv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
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; CHECK-LABEL: test_vminv_s16_used_by_laneop:
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; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a2)
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%1 = trunc i32 %0 to i16
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%2 = insertelement <4 x i16> %a1, i16 %1, i32 3
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ret <4 x i16> %2
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}
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define <2 x i32> @test_vminv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
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; CHECK-LABEL: test_vminv_s32_used_by_laneop:
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; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1
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; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a2)
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%1 = insertelement <2 x i32> %a1, i32 %0, i32 1
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ret <2 x i32> %1
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}
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define <16 x i8> @test_vminvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
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; CHECK-LABEL: test_vminvq_s8_used_by_laneop:
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; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a2)
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%1 = trunc i32 %0 to i8
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%2 = insertelement <16 x i8> %a1, i8 %1, i32 3
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ret <16 x i8> %2
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}
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define <8 x i16> @test_vminvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
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; CHECK-LABEL: test_vminvq_s16_used_by_laneop:
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; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a2)
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%1 = trunc i32 %0 to i16
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%2 = insertelement <8 x i16> %a1, i16 %1, i32 3
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ret <8 x i16> %2
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}
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define <4 x i32> @test_vminvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
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; CHECK-LABEL: test_vminvq_s32_used_by_laneop:
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; CHECK: sminv.4s s[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a2)
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%1 = insertelement <4 x i32> %a1, i32 %0, i32 3
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ret <4 x i32> %1
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}
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declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)
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declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)
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declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)
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declare i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32>)
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declare i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16>)
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declare i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8>)
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