mirror of
https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
208 lines
7.0 KiB
LLVM
208 lines
7.0 KiB
LLVM
; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s
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; ModuleID = 'arm64_vecCmpBr.c'
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
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target triple = "arm64-apple-ios3.0.0"
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define i32 @anyZero64(<4 x i16> %a) #0 {
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; CHECK: _anyZero64:
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; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
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; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
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; CHECK: [[LABEL]]:
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; CHECK-NEXT: b _bar
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entry:
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%0 = bitcast <4 x i16> %a to <8 x i8>
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%vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
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%1 = trunc i32 %vminv.i to i8
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%tobool = icmp eq i8 %1, 0
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br i1 %tobool, label %if.then, label %return
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if.then: ; preds = %entry
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
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br label %return
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return: ; preds = %entry, %if.then
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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declare i32 @bar(...) #1
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define i32 @anyZero128(<8 x i16> %a) #0 {
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; CHECK: _anyZero128:
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; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
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; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
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; CHECK: [[LABEL]]:
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; CHECK-NEXT: b _bar
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entry:
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%0 = bitcast <8 x i16> %a to <16 x i8>
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%vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
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%1 = trunc i32 %vminv.i to i8
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%tobool = icmp eq i8 %1, 0
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br i1 %tobool, label %if.then, label %return
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if.then: ; preds = %entry
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
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br label %return
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return: ; preds = %entry, %if.then
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define i32 @anyNonZero64(<4 x i16> %a) #0 {
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; CHECK: _anyNonZero64:
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; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
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; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
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; CHECK: [[LABEL]]:
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; CHECK-NEXT: movz w0, #0
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entry:
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%0 = bitcast <4 x i16> %a to <8 x i8>
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
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%1 = trunc i32 %vmaxv.i to i8
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%tobool = icmp eq i8 %1, 0
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br i1 %tobool, label %return, label %if.then
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if.then: ; preds = %entry
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
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br label %return
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return: ; preds = %entry, %if.then
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define i32 @anyNonZero128(<8 x i16> %a) #0 {
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; CHECK: _anyNonZero128:
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; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
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; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
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; CHECK: [[LABEL]]:
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; CHECK-NEXT: movz w0, #0
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entry:
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%0 = bitcast <8 x i16> %a to <16 x i8>
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
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%1 = trunc i32 %vmaxv.i to i8
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%tobool = icmp eq i8 %1, 0
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br i1 %tobool, label %return, label %if.then
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if.then: ; preds = %entry
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
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br label %return
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return: ; preds = %entry, %if.then
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define i32 @allZero64(<4 x i16> %a) #0 {
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; CHECK: _allZero64:
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; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0
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; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
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; CHECK: [[LABEL]]:
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; CHECK-NEXT: b _bar
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entry:
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%0 = bitcast <4 x i16> %a to <8 x i8>
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3
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%1 = trunc i32 %vmaxv.i to i8
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%tobool = icmp eq i8 %1, 0
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br i1 %tobool, label %if.then, label %return
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if.then: ; preds = %entry
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
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br label %return
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return: ; preds = %entry, %if.then
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define i32 @allZero128(<8 x i16> %a) #0 {
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; CHECK: _allZero128:
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; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0
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; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
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; CHECK: [[LABEL]]:
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; CHECK-NEXT: b _bar
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entry:
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%0 = bitcast <8 x i16> %a to <16 x i8>
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3
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%1 = trunc i32 %vmaxv.i to i8
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%tobool = icmp eq i8 %1, 0
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br i1 %tobool, label %if.then, label %return
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if.then: ; preds = %entry
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
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br label %return
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return: ; preds = %entry, %if.then
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define i32 @allNonZero64(<4 x i16> %a) #0 {
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; CHECK: _allNonZero64:
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; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
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; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
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; CHECK: [[LABEL]]:
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; CHECK-NEXT: movz w0, #0
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entry:
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%0 = bitcast <4 x i16> %a to <8 x i8>
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%vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
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%1 = trunc i32 %vminv.i to i8
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%tobool = icmp eq i8 %1, 0
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br i1 %tobool, label %return, label %if.then
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if.then: ; preds = %entry
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
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br label %return
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return: ; preds = %entry, %if.then
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define i32 @allNonZero128(<8 x i16> %a) #0 {
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; CHECK: _allNonZero128:
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; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
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; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]]
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; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]]
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; CHECK: [[LABEL]]:
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; CHECK-NEXT: movz w0, #0
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entry:
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%0 = bitcast <8 x i16> %a to <16 x i8>
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%vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
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%1 = trunc i32 %vminv.i to i8
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%tobool = icmp eq i8 %1, 0
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br i1 %tobool, label %return, label %if.then
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if.then: ; preds = %entry
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4
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br label %return
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return: ; preds = %entry, %if.then
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) #2
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declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) #2
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declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) #2
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declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) #2
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attributes #0 = { nounwind ssp "target-cpu"="cyclone" }
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attributes #1 = { "target-cpu"="cyclone" }
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attributes #2 = { nounwind readnone }
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attributes #3 = { nounwind }
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attributes #4 = { nobuiltin nounwind }
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