mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
26d628d6ce
Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230775 91177308-0d34-0410-b5e6-96231b3b80d8
317 lines
9.1 KiB
LLVM
317 lines
9.1 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
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; First test the different supported value types for select.
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define zeroext i1 @select_i1(i1 zeroext %c, i1 zeroext %a, i1 zeroext %b) {
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; CHECK-LABEL: select_i1
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; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne
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%1 = select i1 %c, i1 %a, i1 %b
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ret i1 %1
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}
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define zeroext i8 @select_i8(i1 zeroext %c, i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: select_i8
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; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne
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%1 = select i1 %c, i8 %a, i8 %b
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ret i8 %1
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}
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define zeroext i16 @select_i16(i1 zeroext %c, i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: select_i16
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; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne
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%1 = select i1 %c, i16 %a, i16 %b
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ret i16 %1
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}
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define i32 @select_i32(i1 zeroext %c, i32 %a, i32 %b) {
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; CHECK-LABEL: select_i32
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; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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; CHECK-NEXT: csel {{w[0-9]+}}, w1, w2, ne
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%1 = select i1 %c, i32 %a, i32 %b
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ret i32 %1
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}
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define i64 @select_i64(i1 zeroext %c, i64 %a, i64 %b) {
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; CHECK-LABEL: select_i64
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; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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; CHECK-NEXT: csel {{x[0-9]+}}, x1, x2, ne
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%1 = select i1 %c, i64 %a, i64 %b
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ret i64 %1
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}
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define float @select_f32(i1 zeroext %c, float %a, float %b) {
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; CHECK-LABEL: select_f32
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; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ne
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%1 = select i1 %c, float %a, float %b
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ret float %1
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}
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define double @select_f64(i1 zeroext %c, double %a, double %b) {
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; CHECK-LABEL: select_f64
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; CHECK: {{cmp w0, #0|tst w0, #0x1}}
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; CHECK-NEXT: fcsel {{d[0-9]+}}, d0, d1, ne
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%1 = select i1 %c, double %a, double %b
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ret double %1
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}
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; Now test the folding of all compares.
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define float @select_fcmp_false(float %x, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_false
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; CHECK: mov.16b {{v[0-9]+}}, v2
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%1 = fcmp ogt float %x, %x
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_ogt(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_ogt
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, gt
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%1 = fcmp ogt float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_oge(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_oge
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ge
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%1 = fcmp oge float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_olt(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_olt
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, mi
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%1 = fcmp olt float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_ole(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_ole
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ls
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%1 = fcmp ole float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_one(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_one
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel [[REG:s[0-9]+]], s2, s3, mi
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, [[REG]], gt
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%1 = fcmp one float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_ord(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_ord
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, vc
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%1 = fcmp ord float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_uno(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_uno
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, vs
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%1 = fcmp uno float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_ueq(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_ueq
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel [[REG:s[0-9]+]], s2, s3, eq
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, [[REG]], vs
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%1 = fcmp ueq float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_ugt(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_ugt
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, hi
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%1 = fcmp ugt float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_uge(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_uge
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, pl
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%1 = fcmp uge float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_ult(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_ult
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, lt
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%1 = fcmp ult float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_ule(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_ule
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, le
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%1 = fcmp ule float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_une(float %x, float %y, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_une
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s2, s3, ne
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%1 = fcmp une float %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_fcmp_true(float %x, float %a, float %b) {
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; CHECK-LABEL: select_fcmp_true
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; CHECK: mov.16b {{v[0-9]+}}, v1
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%1 = fcmp ueq float %x, %x
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_icmp_eq(i32 %x, i32 %y, float %a, float %b) {
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; CHECK-LABEL: select_icmp_eq
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; CHECK: cmp w0, w1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, eq
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%1 = icmp eq i32 %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_icmp_ne(i32 %x, i32 %y, float %a, float %b) {
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; CHECK-LABEL: select_icmp_ne
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; CHECK: cmp w0, w1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ne
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%1 = icmp ne i32 %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_icmp_ugt(i32 %x, i32 %y, float %a, float %b) {
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; CHECK-LABEL: select_icmp_ugt
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; CHECK: cmp w0, w1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, hi
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%1 = icmp ugt i32 %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_icmp_uge(i32 %x, i32 %y, float %a, float %b) {
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; CHECK-LABEL: select_icmp_uge
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; CHECK: cmp w0, w1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, hs
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%1 = icmp uge i32 %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_icmp_ult(i32 %x, i32 %y, float %a, float %b) {
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; CHECK-LABEL: select_icmp_ult
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; CHECK: cmp w0, w1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, lo
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%1 = icmp ult i32 %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_icmp_ule(i32 %x, i32 %y, float %a, float %b) {
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; CHECK-LABEL: select_icmp_ule
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; CHECK: cmp w0, w1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ls
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%1 = icmp ule i32 %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_icmp_sgt(i32 %x, i32 %y, float %a, float %b) {
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; CHECK-LABEL: select_icmp_sgt
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; CHECK: cmp w0, w1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, gt
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%1 = icmp sgt i32 %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_icmp_sge(i32 %x, i32 %y, float %a, float %b) {
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; CHECK-LABEL: select_icmp_sge
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; CHECK: cmp w0, w1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, ge
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%1 = icmp sge i32 %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_icmp_slt(i32 %x, i32 %y, float %a, float %b) {
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; CHECK-LABEL: select_icmp_slt
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; CHECK: cmp w0, w1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, lt
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%1 = icmp slt i32 %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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define float @select_icmp_sle(i32 %x, i32 %y, float %a, float %b) {
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; CHECK-LABEL: select_icmp_sle
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; CHECK: cmp w0, w1
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; CHECK-NEXT: fcsel {{s[0-9]+}}, s0, s1, le
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%1 = icmp sle i32 %x, %y
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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; Test peephole optimizations for select.
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define zeroext i1 @select_opt1(i1 zeroext %c, i1 zeroext %a) {
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; CHECK-LABEL: select_opt1
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; CHECK: orr {{w[0-9]+}}, w0, w1
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%1 = select i1 %c, i1 true, i1 %a
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ret i1 %1
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}
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define zeroext i1 @select_opt2(i1 zeroext %c, i1 zeroext %a) {
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; CHECK-LABEL: select_opt2
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; CHECK: eor [[REG:w[0-9]+]], w0, #0x1
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; CHECK: orr {{w[0-9]+}}, [[REG]], w1
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%1 = select i1 %c, i1 %a, i1 true
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ret i1 %1
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}
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define zeroext i1 @select_opt3(i1 zeroext %c, i1 zeroext %a) {
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; CHECK-LABEL: select_opt3
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; CHECK: bic {{w[0-9]+}}, w1, w0
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%1 = select i1 %c, i1 false, i1 %a
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ret i1 %1
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}
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define zeroext i1 @select_opt4(i1 zeroext %c, i1 zeroext %a) {
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; CHECK-LABEL: select_opt4
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; CHECK: and {{w[0-9]+}}, w0, w1
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%1 = select i1 %c, i1 %a, i1 false
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ret i1 %1
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}
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