mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
b7db5f28c5
Summary: Set operation action for SINT_TO_FP and UINT_TO_FP nodes with v4i32, v8i8, v8i16 inputs to allow promotion of v4f16 results. Add tests for sitofp and uitofp for vec4, vec8, vec16, and i8, i16, i32, and i64 vectors. Only missing tests are for v16i8 and v16i16 as the shift operations are too complicated to write a proper check sequence. The conversions from v4i64 to v4f16 do not depend on this patch - v4i64 is split and the conversion gets handled while lowering v2i64. I am adding a test here for completeness. Reviewers: aemerson, rengolin, ab, jmolloy, srhines Subscribers: rengolin, aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D9166 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235609 91177308-0d34-0410-b5e6-96231b3b80d8
222 lines
5.5 KiB
LLVM
222 lines
5.5 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s
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define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {
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entry:
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; CHECK-LABEL: add_h:
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; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
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; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
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; CHECK: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
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; CHECK: fcvtn v0.4h, [[RES]]
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%0 = fadd <4 x half> %a, %b
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ret <4 x half> %0
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}
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define <4 x half> @build_h4(<4 x half> %a) {
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entry:
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; CHECK-LABEL: build_h4:
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; CHECK: movz [[GPR:w[0-9]+]], #0x3ccd
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; CHECK: dup v0.4h, [[GPR]]
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ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD>
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}
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define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) {
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entry:
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; CHECK-LABEL: sub_h:
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; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
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; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
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; CHECK: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
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; CHECK: fcvtn v0.4h, [[RES]]
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%0 = fsub <4 x half> %a, %b
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ret <4 x half> %0
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}
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define <4 x half> @mul_h(<4 x half> %a, <4 x half> %b) {
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entry:
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; CHECK-LABEL: mul_h:
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; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
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; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
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; CHECK: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
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; CHECK: fcvtn v0.4h, [[RES]]
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%0 = fmul <4 x half> %a, %b
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ret <4 x half> %0
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}
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define <4 x half> @div_h(<4 x half> %a, <4 x half> %b) {
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entry:
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; CHECK-LABEL: div_h:
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; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
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; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
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; CHECK: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
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; CHECK: fcvtn v0.4h, [[RES]]
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%0 = fdiv <4 x half> %a, %b
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ret <4 x half> %0
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}
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define <4 x half> @load_h(<4 x half>* %a) {
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entry:
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; CHECK-LABEL: load_h:
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; CHECK: ldr d0, [x0]
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%0 = load <4 x half>, <4 x half>* %a, align 4
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ret <4 x half> %0
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}
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define void @store_h(<4 x half>* %a, <4 x half> %b) {
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entry:
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; CHECK-LABEL: store_h:
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; CHECK: str d0, [x0]
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store <4 x half> %b, <4 x half>* %a, align 4
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ret void
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}
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define <4 x half> @s_to_h(<4 x float> %a) {
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; CHECK-LABEL: s_to_h:
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; CHECK: fcvtn v0.4h, v0.4s
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%1 = fptrunc <4 x float> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @d_to_h(<4 x double> %a) {
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; CHECK-LABEL: d_to_h:
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; CHECK-DAG: fcvt
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; CHECK-DAG: fcvt
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; CHECK-DAG: fcvt
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; CHECK-DAG: fcvt
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; CHECK-DAG: ins
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; CHECK-DAG: ins
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; CHECK-DAG: ins
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; CHECK-DAG: ins
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%1 = fptrunc <4 x double> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x float> @h_to_s(<4 x half> %a) {
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; CHECK-LABEL: h_to_s:
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; CHECK: fcvtl v0.4s, v0.4h
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%1 = fpext <4 x half> %a to <4 x float>
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ret <4 x float> %1
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}
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define <4 x double> @h_to_d(<4 x half> %a) {
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; CHECK-LABEL: h_to_d:
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; CHECK-DAG: fcvt
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; CHECK-DAG: fcvt
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; CHECK-DAG: fcvt
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; CHECK-DAG: fcvt
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; CHECK-DAG: ins
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; CHECK-DAG: ins
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; CHECK-DAG: ins
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; CHECK-DAG: ins
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%1 = fpext <4 x half> %a to <4 x double>
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ret <4 x double> %1
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}
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define <4 x half> @bitcast_i_to_h(float, <4 x i16> %a) {
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; CHECK-LABEL: bitcast_i_to_h:
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; CHECK: mov v0.16b, v1.16b
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%2 = bitcast <4 x i16> %a to <4 x half>
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ret <4 x half> %2
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}
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define <4 x i16> @bitcast_h_to_i(float, <4 x half> %a) {
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; CHECK-LABEL: bitcast_h_to_i:
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; CHECK: mov v0.16b, v1.16b
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%2 = bitcast <4 x half> %a to <4 x i16>
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ret <4 x i16> %2
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}
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define <4 x half> @sitofp_i8(<4 x i8> %a) #0 {
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; CHECK-LABEL: sitofp_i8:
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; CHECK-NEXT: shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
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; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
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; CHECK-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
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; CHECK-NEXT: scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
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; CHECK-NEXT: fcvtn v0.4h, [[OP4]]
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; CHECK-NEXT: ret
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%1 = sitofp <4 x i8> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @sitofp_i16(<4 x i16> %a) #0 {
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; CHECK-LABEL: sitofp_i16:
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; CHECK-NEXT: sshll [[OP1:v[0-9]+\.4s]], v0.4h, #0
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; CHECK-NEXT: scvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
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; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
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; CHECK-NEXT: ret
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%1 = sitofp <4 x i16> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @sitofp_i32(<4 x i32> %a) #0 {
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; CHECK-LABEL: sitofp_i32:
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; CHECK-NEXT: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
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; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
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%1 = sitofp <4 x i32> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @sitofp_i64(<4 x i64> %a) #0 {
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; CHECK-LABEL: sitofp_i64:
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; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
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; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
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; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
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; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
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; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
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%1 = sitofp <4 x i64> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @uitofp_i8(<4 x i8> %a) #0 {
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; CHECK-LABEL: uitofp_i8:
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; CHECK-NEXT: bic v0.4h, #0xff, lsl #8
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; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
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; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
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; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
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; CHECK-NEXT: ret
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%1 = uitofp <4 x i8> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @uitofp_i16(<4 x i16> %a) #0 {
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; CHECK-LABEL: uitofp_i16:
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; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
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; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
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; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
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; CHECK-NEXT: ret
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%1 = uitofp <4 x i16> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @uitofp_i32(<4 x i32> %a) #0 {
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; CHECK-LABEL: uitofp_i32:
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; CHECK-NEXT: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
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; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
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%1 = uitofp <4 x i32> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @uitofp_i64(<4 x i64> %a) #0 {
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; CHECK-LABEL: uitofp_i64:
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; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
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; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
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; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
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; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
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; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
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%1 = uitofp <4 x i64> %a to <4 x half>
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ret <4 x half> %1
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}
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attributes #0 = { nounwind }
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