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https://github.com/c64scene-ar/llvm-6502.git
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d90099d36c
The test here was sinking the AND here to a lower BB: %vreg7<def> = ANDWri %vreg8, 0; GPR32common:%vreg7,%vreg8 TBNZW %vreg8<kill>, 0, <BB#1>; GPR32common:%vreg8 which meant that vreg8 was read after it was killed. This commit changes the code from clearing kill flags on the AND to clearing flags on all registers used by the AND. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236886 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
939 B
LLVM
30 lines
939 B
LLVM
; RUN: llc %s -o - -fast-isel=true -O1 -verify-machineinstrs | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-ios8.0.0"
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; The machine verifier was asserting on this test because the AND instruction was
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; sunk below the test which killed %tmp340.
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; The kill flags on the test had to be cleared because the AND was going to read
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; registers in a BB after the test instruction.
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; CHECK: %bb343
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; CHECK: and
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define i32 @test(i32* %ptr) {
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bb:
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br label %.thread
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.thread: ; preds = %.thread, %bb
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%loc = phi i32 [ %next_iter, %.thread ], [ 0, %bb ]
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%next_iter = lshr i32 %loc, 1
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%tmp340 = sub i32 %loc, 1
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%tmp341 = and i32 %tmp340, 1
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%tmp342 = icmp eq i32 %tmp341, 0
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br i1 %tmp342, label %bb343, label %.thread
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bb343: ; preds = %.thread
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store i32 %tmp341, i32* %ptr, align 4
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ret i32 -1
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}
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