mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.8 KiB
LLVM
58 lines
1.8 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; A vector TruncStore can not be selected.
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; Test a trunc IR and a vector store IR can be selected correctly.
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define void @truncStore.v2i64(<2 x i64> %a, <2 x i32>* %result) {
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; CHECK-LABEL: truncStore.v2i64:
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; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
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; CHECK: {{st1 { v[0-9]+.2s }|str d[0-9]+}}, [x{{[0-9]+|sp}}]
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%b = trunc <2 x i64> %a to <2 x i32>
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store <2 x i32> %b, <2 x i32>* %result
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ret void
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}
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define void @truncStore.v4i32(<4 x i32> %a, <4 x i16>* %result) {
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; CHECK-LABEL: truncStore.v4i32:
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; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
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; CHECK: {{st1 { v[0-9]+.4h }|str d[0-9]+}}, [x{{[0-9]+|sp}}]
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%b = trunc <4 x i32> %a to <4 x i16>
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store <4 x i16> %b, <4 x i16>* %result
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ret void
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}
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define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) {
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; CHECK-LABEL: truncStore.v8i16:
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; CHECK: xtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h
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; CHECK: {{st1 { v[0-9]+.8b }|str d[0-9]+}}, [x{{[0-9]+|sp}}]
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%b = trunc <8 x i16> %a to <8 x i8>
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store <8 x i8> %b, <8 x i8>* %result
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ret void
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}
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; A vector LoadExt can not be selected.
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; Test a vector load IR and a sext/zext IR can be selected correctly.
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define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) {
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; CHECK-LABEL: loadSExt.v4i8:
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; CHECK: ldrsb
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%a = load <4 x i8>, <4 x i8>* %ref
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%conv = sext <4 x i8> %a to <4 x i32>
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ret <4 x i32> %conv
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}
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define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) {
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; CHECK-LABEL: loadZExt.v4i8:
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; CHECK: ldrb
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%a = load <4 x i8>, <4 x i8>* %ref
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%conv = zext <4 x i8> %a to <4 x i32>
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ret <4 x i32> %conv
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}
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define i32 @loadExt.i32(<4 x i8>* %ref) {
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; CHECK-LABEL: loadExt.i32:
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; CHECK: ldrb
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%a = load <4 x i8>, <4 x i8>* %ref
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%vecext = extractelement <4 x i8> %a, i32 0
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%conv = zext i8 %vecext to i32
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ret i32 %conv
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}
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