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0966a4e370
Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp load balancing pass isn't enabled for Cortex-A72 as it's not profitable to have it enabled for this core. Patch by Ranjeet Singh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228140 91177308-0d34-0410-b5e6-96231b3b80d8
18 lines
509 B
LLVM
18 lines
509 B
LLVM
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s
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%X = type { i64, i64, i64 }
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declare void @f(%X*)
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define void @t() {
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entry:
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%tmp = alloca %X
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call void @f(%X* %tmp)
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; CHECK: add x0, sp, #8
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; CHECK-NEXT-NOT: mov
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call void @f(%X* %tmp)
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; CHECK: add x0, sp, #8
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; CHECK-NEXT-NOT: mov
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ret void
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}
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