mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
912e816cc2
Summary: We identify the cases where the operand to an ADDE node is a constant zero. In such cases, we can avoid generating an extra ADDu instruction disguised as an identity move alias (ie. addu $r, $r, 0 --> move $r, $r). Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7906 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230742 91177308-0d34-0410-b5e6-96231b3b80d8
36 lines
1.4 KiB
LLVM
36 lines
1.4 KiB
LLVM
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
|
|
; RUN: -check-prefix=ALL -check-prefix=GP32
|
|
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
|
|
; RUN: -check-prefix=ALL -check-prefix=GP32
|
|
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
|
|
; RUN: -check-prefix=ALL -check-prefix=GP32
|
|
; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
|
|
; RUN: -check-prefix=ALL -check-prefix=GP32
|
|
; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
|
|
; RUN: -check-prefix=ALL -check-prefix=GP32
|
|
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
|
|
; RUN: -check-prefix=ALL -check-prefix=GP32
|
|
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefix=ALL
|
|
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL
|
|
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL
|
|
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL
|
|
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL
|
|
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL
|
|
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL
|
|
|
|
define i64 @add_i64(i64 %a) {
|
|
; GP32-LABEL: add_i64
|
|
|
|
; GP32-NOT: move $[[T0:[0-9]+]], $[[T0]]
|
|
%r = add i64 5, %a
|
|
ret i64 %r
|
|
}
|
|
|
|
define i128 @add_i128(i128 %a) {
|
|
; ALL-LABEL: add_i128
|
|
|
|
; ALL-NOT: move $[[T0:[0-9]+]], $[[T0]]
|
|
%r = add i128 5, %a
|
|
ret i128 %r
|
|
}
|