mirror of
https://github.com/c64scene-ar/llvm-6502.git
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330e5f16d1
Summary: With this change we are able to realign the stack dynamically, whenever it contains objects with alignment requirements that are larger than the alignment specified from the given ABI. We have to use the $fp register as the frame pointer when we perform dynamic stack realignment. In complex stack frames, with variably-sized objects, we reserve additionally the callee-saved register $s7 as the base pointer in order to reference locals. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8633 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238829 91177308-0d34-0410-b5e6-96231b3b80d8
33 lines
1.3 KiB
LLVM
33 lines
1.3 KiB
LLVM
; Check that register scavenging spill slot is close to $fp.
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; RUN: llc -march=mipsel -O0 < %s | FileCheck %s
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; CHECK: sw ${{.*}}, 4($sp)
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; CHECK: lw ${{.*}}, 4($sp)
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define i32 @main(i32 signext %argc, i8** %argv) "no-frame-pointer-elim"="true" {
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entry:
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%retval = alloca i32, align 4
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%argc.addr = alloca i32, align 4
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%argv.addr = alloca i8**, align 4
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%v0 = alloca <16 x i8>, align 16
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%.compoundliteral = alloca <16 x i8>, align 16
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%v1 = alloca <16 x i8>, align 16
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%.compoundliteral1 = alloca <16 x i8>, align 16
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%unused_variable = alloca [16384 x i32], align 4
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%result = alloca <16 x i8>, align 16
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store i32 0, i32* %retval
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store i32 %argc, i32* %argc.addr, align 4
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store i8** %argv, i8*** %argv.addr, align 4
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store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %.compoundliteral
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%0 = load <16 x i8>, <16 x i8>* %.compoundliteral
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store <16 x i8> %0, <16 x i8>* %v0, align 16
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store <16 x i8> zeroinitializer, <16 x i8>* %.compoundliteral1
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%1 = load <16 x i8>, <16 x i8>* %.compoundliteral1
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store <16 x i8> %1, <16 x i8>* %v1, align 16
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%2 = load <16 x i8>, <16 x i8>* %v0, align 16
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%3 = load <16 x i8>, <16 x i8>* %v1, align 16
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%mul = mul <16 x i8> %2, %3
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store <16 x i8> %mul, <16 x i8>* %result, align 16
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ret i32 0
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}
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