mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
5a70dd1d82
Similar to gep (r230786) and load (r230794) changes.
Similar migration script can be used to update test cases, which
successfully migrated all of LLVM and Polly, but about 4 test cases
needed manually changes in Clang.
(this script will read the contents of stdin and massage it into stdout
- wrap it in the 'apply.sh' script shown in previous commits + xargs to
apply it over a large set of test cases)
import fileinput
import sys
import re
rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL)
def conv(match):
line = match.group(1)
line += match.group(4)
line += ", "
line += match.group(2)
return line
line = sys.stdin.read()
off = 0
for match in re.finditer(rep, line):
sys.stdout.write(line[off:match.start()])
sys.stdout.write(conv(match))
off = match.end()
sys.stdout.write(line[off:])
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232184 91177308-0d34-0410-b5e6-96231b3b80d8
263 lines
7.1 KiB
LLVM
263 lines
7.1 KiB
LLVM
; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R1
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R2
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; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R6
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; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
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; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
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; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
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; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64R6
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; Check that [ls][dwu]xc1 are not emitted for nacl.
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; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=CHECK-NACL
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%struct.S = type <{ [4 x float] }>
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%struct.S2 = type <{ [4 x double] }>
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%struct.S3 = type <{ i8, float }>
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@s = external global [4 x %struct.S]
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@gf = external global float
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@gd = external global double
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@s2 = external global [4 x %struct.S2]
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@s3 = external global %struct.S3
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define float @foo0(float* nocapture %b, i32 %o) nounwind readonly {
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entry:
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; ALL-LABEL: foo0:
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; MIPS32R1: sll $[[T1:[0-9]+]], $5, 2
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; MIPS32R1: addu $[[T3:[0-9]+]], $4, $[[T1]]
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; MIPS32R1: lwc1 $f0, 0($[[T3]])
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; MIPS32R2: sll $[[T1:[0-9]+]], $5, 2
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; MIPS32R2: lwxc1 $f0, $[[T1]]($4)
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; MIPS32R6: sll $[[T1:[0-9]+]], $5, 2
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; MIPS32R6: addu $[[T3:[0-9]+]], $4, $[[T1]]
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; MIPS32R6: lwc1 $f0, 0($[[T3]])
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; MIPS4: sll $[[T0:[0-9]+]], $5, 0
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; MIPS4: dsll $[[T1:[0-9]+]], $[[T0]], 2
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; MIPS4: lwxc1 $f0, $[[T1]]($4)
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; MIPS64R6: sll $[[T0:[0-9]+]], $5, 0
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; MIPS64R6: dsll $[[T1:[0-9]+]], $[[T0]], 2
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; MIPS64R6: daddu $[[T3:[0-9]+]], $4, $[[T1]]
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; MIPS64R6: lwc1 $f0, 0($[[T3]])
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; CHECK-NACL-NOT: lwxc1
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%arrayidx = getelementptr inbounds float, float* %b, i32 %o
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%0 = load float, float* %arrayidx, align 4
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ret float %0
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}
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define double @foo1(double* nocapture %b, i32 %o) nounwind readonly {
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entry:
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; ALL-LABEL: foo1:
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; MIPS32R1: sll $[[T1:[0-9]+]], $5, 3
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; MIPS32R1: addu $[[T3:[0-9]+]], $4, $[[T1]]
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; MIPS32R1: ldc1 $f0, 0($[[T3]])
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; MIPS32R2: sll $[[T1:[0-9]+]], $5, 3
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; MIPS32R2: ldxc1 $f0, $[[T1]]($4)
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; MIPS32R6: sll $[[T1:[0-9]+]], $5, 3
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; MIPS32R6: addu $[[T3:[0-9]+]], $4, $[[T1]]
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; MIPS32R6: ldc1 $f0, 0($[[T3]])
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; MIPS4: sll $[[T0:[0-9]+]], $5, 0
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; MIPS4: dsll $[[T1:[0-9]+]], $[[T0]], 3
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; MIPS4: ldxc1 $f0, $[[T1]]($4)
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; MIPS64R6: sll $[[T0:[0-9]+]], $5, 0
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; MIPS64R6: dsll $[[T1:[0-9]+]], $[[T0]], 3
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; MIPS64R6: daddu $[[T3:[0-9]+]], $4, $[[T1]]
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; MIPS64R6: ldc1 $f0, 0($[[T3]])
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; CHECK-NACL-NOT: ldxc1
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%arrayidx = getelementptr inbounds double, double* %b, i32 %o
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%0 = load double, double* %arrayidx, align 8
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ret double %0
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}
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define float @foo2(i32 %b, i32 %c) nounwind readonly {
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entry:
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; ALL-LABEL: foo2:
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; luxc1 did not exist in MIPS32r1
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; MIPS32R1-NOT: luxc1
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; luxc1 is a misnomer since it aligns the given pointer downwards and performs
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; an aligned load. We mustn't use it to handle unaligned loads.
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; MIPS32R2-NOT: luxc1
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; luxc1 was removed in MIPS32r6
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; MIPS32R6-NOT: luxc1
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; MIPS4-NOT: luxc1
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; luxc1 was removed in MIPS64r6
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; MIPS64R6-NOT: luxc1
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%arrayidx1 = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
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%0 = load float, float* %arrayidx1, align 1
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ret float %0
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}
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define void @foo3(float* nocapture %b, i32 %o) nounwind {
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entry:
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; ALL-LABEL: foo3:
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; MIPS32R1-DAG: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS32R1-DAG: addu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
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; MIPS32R1-DAG: swc1 $[[T0]], 0($[[T1]])
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; MIPS32R2: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS32R2: swxc1 $[[T0]], ${{[0-9]+}}($4)
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; MIPS32R6-DAG: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS32R6-DAG: addu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
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; MIPS32R6-DAG: swc1 $[[T0]], 0($[[T1]])
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; MIPS4: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS4: swxc1 $[[T0]], ${{[0-9]+}}($4)
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; MIPS64R6-DAG: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS64R6-DAG: daddu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
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; MIPS64R6-DAG: swc1 $[[T0]], 0($[[T1]])
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; CHECK-NACL-NOT: swxc1
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%0 = load float, float* @gf, align 4
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%arrayidx = getelementptr inbounds float, float* %b, i32 %o
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store float %0, float* %arrayidx, align 4
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ret void
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}
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define void @foo4(double* nocapture %b, i32 %o) nounwind {
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entry:
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; ALL-LABEL: foo4:
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; MIPS32R1-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS32R1-DAG: addu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
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; MIPS32R1-DAG: sdc1 $[[T0]], 0($[[T1]])
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; MIPS32R2: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS32R2: sdxc1 $[[T0]], ${{[0-9]+}}($4)
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; MIPS32R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS32R6-DAG: addu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
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; MIPS32R6-DAG: sdc1 $[[T0]], 0($[[T1]])
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; MIPS4: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS4: sdxc1 $[[T0]], ${{[0-9]+}}($4)
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; MIPS64R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
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; MIPS64R6-DAG: daddu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
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; MIPS64R6-DAG: sdc1 $[[T0]], 0($[[T1]])
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; CHECK-NACL-NOT: sdxc1
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%0 = load double, double* @gd, align 8
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%arrayidx = getelementptr inbounds double, double* %b, i32 %o
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store double %0, double* %arrayidx, align 8
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ret void
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}
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define void @foo5(i32 %b, i32 %c) nounwind {
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entry:
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; ALL-LABEL: foo5:
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; MIPS32R1-NOT: suxc1
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; MIPS32R2-NOT: suxc1
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; MIPS32R6-NOT: suxc1
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; MIPS4-NOT: suxc1
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; MIPS64R6-NOT: suxc1
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%0 = load float, float* @gf, align 4
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%arrayidx1 = getelementptr inbounds [4 x %struct.S], [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
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store float %0, float* %arrayidx1, align 1
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ret void
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}
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define double @foo6(i32 %b, i32 %c) nounwind readonly {
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entry:
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; ALL-LABEL: foo6:
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; MIPS32R1-NOT: luxc1
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; MIPS32R2-NOT: luxc1
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; MIPS32R6-NOT: luxc1
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; MIPS4-NOT: luxc1
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; MIPS64R6-NOT: luxc1
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%arrayidx1 = getelementptr inbounds [4 x %struct.S2], [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
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%0 = load double, double* %arrayidx1, align 1
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ret double %0
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}
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define void @foo7(i32 %b, i32 %c) nounwind {
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entry:
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; ALL-LABEL: foo7:
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; MIPS32R1-NOT: suxc1
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; MIPS32R2-NOT: suxc1
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; MIPS32R6-NOT: suxc1
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; MIPS4-NOT: suxc1
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; MIPS64R6-NOT: suxc1
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%0 = load double, double* @gd, align 8
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%arrayidx1 = getelementptr inbounds [4 x %struct.S2], [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
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store double %0, double* %arrayidx1, align 1
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ret void
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}
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define float @foo8() nounwind readonly {
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entry:
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; ALL-LABEL: foo8:
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; MIPS32R1-NOT: luxc1
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; MIPS32R2-NOT: luxc1
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; MIPS32R6-NOT: luxc1
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; MIPS4-NOT: luxc1
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; MIPS64R6-NOT: luxc1
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%0 = load float, float* getelementptr inbounds (%struct.S3, %struct.S3* @s3, i32 0, i32 1), align 1
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ret float %0
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}
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define void @foo9(float %f) nounwind {
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entry:
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; ALL-LABEL: foo9:
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; MIPS32R1-NOT: suxc1
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; MIPS32R2-NOT: suxc1
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; MIPS32R6-NOT: suxc1
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; MIPS4-NOT: suxc1
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; MIPS64R6-NOT: suxc1
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store float %f, float* getelementptr inbounds (%struct.S3, %struct.S3* @s3, i32 0, i32 1), align 1
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ret void
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}
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