llvm-6502/test/CodeGen/Mips/micromips-sw-lw-16.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

28 lines
910 B
LLVM

; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm \
; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
; Function Attrs: noinline nounwind
define void @bar(i32* %p) #0 {
entry:
%p.addr = alloca i32*, align 4
store i32* %p, i32** %p.addr, align 4
%0 = load i32*, i32** %p.addr, align 4
%1 = load i32, i32* %0, align 4
%add = add nsw i32 7, %1
%2 = load i32*, i32** %p.addr, align 4
store i32 %add, i32* %2, align 4
%3 = load i32*, i32** %p.addr, align 4
%add.ptr = getelementptr inbounds i32, i32* %3, i32 1
%4 = load i32, i32* %add.ptr, align 4
%add1 = add nsw i32 7, %4
%5 = load i32*, i32** %p.addr, align 4
%add.ptr2 = getelementptr inbounds i32, i32* %5, i32 1
store i32 %add1, i32* %add.ptr2, align 4
ret void
}
; CHECK: lw16 ${{[0-9]+}}, 0($4)
; CHECK: sw16 ${{[0-9]+}}, 0($4)
; CHECK: lw16 ${{[0-9]+}}, 4(${{[0-9]+}})
; CHECK: sw16 ${{[0-9]+}}, 4(${{[0-9]+}})